Stacked Memory Chip Multiplexing for Reduced Package I/O

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Solution Overview

Problem

The high number of I/Os in traditional stacked memory chip solutions, such as HBM, leads to increased packaging costs and complexity due to the need for sophisticated technologies like EMIB and finer pitch wires, limiting memory capacity without significant cost reduction.

Innovation Solution

Implementing multiplexers in the base logic chip to reduce the number of external channels by using multiplexing schemes, such as 4:1, and reducing internal channel width, allowing for higher memory capacity with reduced packaging costs and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional stacked memory chip solutions are used with dedicated memory channels for each memory chip half, then memory capacity can be increased, but the number of I/Os increases significantly leading to increased packaging costs and complexity

Engineering Contradiction:

Improvememory capacityVSAvoidpackaging complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

Multiple memory chip halves that would traditionally have dedicated dedicated channels are merged and shared through a common set of external channels. The base logic chip includes multiplexers that allow multiple internal channels to share external channels, reducing the total number of I/Os required while maintaining the ability to access all memory chips.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The external channels are designed to serve multiple internal channels through multiplexing. Each external channel can be dynamically assigned to different internal channels based on timing signals, making the external channels universal rather than dedicated to a single memory chip half.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If traditional stacked memory chip solutions with dedicated channels are used, then memory capacity increases, but the number of I/Os increases requiring sophisticated packaging technologies like EMIB and finer pitch wires

Engineering Contradiction:

Improvememory capacityVSAvoidpackaging manufacturing

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If the number of external channels is reduced through multiplexing, then packaging costs and complexity are reduced, but the internal channel width must be reduced

Engineering Contradiction:

Improvepackaging complexityVSAvoidinternal channel width

Core Design Contradiction:

Device complexityVSQuantity of substance

Solution Approach 1:

The channel configuration is dynamic rather than static. The multiplexers in the base logic chip can switch connections based on timing signals, allowing the same physical external channel to serve different internal channels at different times. This dynamic multiplexing enables reduced external channel count without permanently reducing internal channel capacity.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250349327A1Stacked memory chip solution with reduced package inputs/outputs (i/os)

Publication Date: 2025.11.13 INTEL CORP

AI summary

An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.