Word Line Leakage Detection for Faster Memory Cell Testing
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Solution Overview
Problem
Existing memory detection methods for volatile memory devices, such as DRAM, require significant time and power due to the need for write and read operations to identify defective memory cells.
Innovation Solution
A memory device and method that detects defective memory cells based on word line leakage current without write or read operations, using a word line defect detection circuit to generate fail flags and store fail row addresses in mode registers, allowing for efficient identification of defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If write and read operations are performed to detect failed memory cells, then detection accuracy is improved, but detection time and power consumption increase significantly
Solution Approach 1:
The patent extracts the detection function from the full write-read operation cycle and isolates it to a dedicated word line defect detection circuit that operates independently. This circuit specifically monitors word line leakage current without requiring complete read/write cycles, thereby reducing detection time while maintaining accuracy.
Solution Approach 2:
The patent introduces a word line defect detection circuit as an intermediary component between the memory controller and the memory cell array. This intermediary circuit performs preliminary detection of word line defects through leakage current measurement, filtering out potential failures before they are detected through full read/write operations.
2Measurement precision
If write and read operations are performed to detect failed memory cells, then detection accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts the power-intensive write and read operations from the detection process and replaces them with a low-power leakage current measurement mechanism. The word line defect detection circuit uses minimal power to monitor voltage changes on word lines without activating the full memory access protocol.
Solution Approach 2:
Instead of performing complete write and read operations (excessive action), the patent applies partial action by only measuring the leakage current state of word lines. This partial measurement approach provides sufficient detection capability without the full power cost of complete read/write cycles.
3Reliability
If a memory controller performs error detection by writing and reading dummy data, then detection reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error detection function from the memory controller and implements it as a dedicated word line defect detection circuit within the memory device. This separation reduces the complexity of the memory controller while maintaining detection reliability through specialized hardware assistance.
Solution Approach 2:
The memory device performs self-diagnosis through the word line defect detection circuit that autonomously monitors for failures without requiring continuous intervention from the memory controller. The circuit automatically detects and reports word line defects, reducing the complexity of controller-based detection algorithms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces time and power consumption in detecting defective memory cells by utilizing word line leakage current to identify defects without write or read operations, enabling faster and more efficient defect detection and restoration.
Implementation Method 1
a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines... generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input/output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.