Flying Bit Line Memory Layout for Lower Load and Coupling
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Solution Overview
Problem
Existing semiconductor memory devices face issues of high loads on bit lines leading to high minimum read and write voltages, instability, and capacitive coupling between closely spaced bit lines, resulting in slow read and write times and increased power consumption.
Innovation Solution
The memory device separates bit lines into multiple segments across different metallization layers, with each bit line being operatively coupled to different portions of the memory bank through fly bit lines in higher metallization layers, reducing load and capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are closely spaced to increase integration density, then more components can be integrated into a given area, but capacitive coupling between bit lines increases causing signal instability and slower read/write times
Solution Approach 1:
The patent transitions bit lines from a two-dimensional planar arrangement to a three-dimensional stacked configuration across multiple metallization layers. Fly bit lines in upper metallization layers connect to segment bit lines in lower layers, enabling vertical signal routing that reduces lateral spacing requirements while maintaining signal integrity and reducing capacitive coupling between adjacent bit lines.
Solution Approach 2:
The bit line structure is divided into multiple segments across different metallization layers. Each bit line is split into segment bit lines in lower layers and connected via fly bit lines in upper layers. This segmentation allows each segment to be independently optimized and reduces the total capacitance loading on each individual bit line segment, improving signal stability.
2Length of moving object
If bit lines are made longer to access more memory cells, then more memory cells can be accessed, but the load on bit lines increases requiring higher minimum read and write voltages
Solution Approach 1:
Long bit lines are divided into multiple shorter segments distributed across different metallization layers. Each segment connects to a portion of the memory bank, reducing the capacitive load on each individual segment. This allows longer overall bit line coverage while maintaining lower voltage requirements for each segment.
Solution Approach 2:
The bit line network extends into the vertical dimension across multiple metallization layers. Fly bit lines in upper layers connect to segment bit lines in lower layers, distributing the loading across three-dimensional space. This reduces the effective load on any single bit line segment compared to a traditional planar configuration.
3Reliability
If more metallization layers are used to separate bit lines, then capacitive coupling is reduced and signal integrity improves, but device complexity increases
Solution Approach 1:
The patent utilizes vertical stacking of metallization layers to separate bit lines in the lateral direction. Fly bit lines in upper metallization layers connect to segment bit lines in lower layers, achieving signal integrity through three-dimensional routing while efficiently using the available vertical space in the device structure.
Data Source
AI summary
A memory device includes a first memory array comprising first memory cells; a second memory array comprising second memory cells; a third memory array comprising third memory cells, the second memory array interposed between the first memory array and the third memory array along a lateral direction; a first bit line segment extending along the lateral direction and coupled to each of the first memory cells; a second bit line segment extending along the lateral direction and coupled to each of the second memory cells; and a third bit line segment extending along the lateral direction and coupled to each of the third memory cells. The first bit line segment is formed in a first metallization layer, the second bit line segment is formed in a second metallization layer, and the third bit line segment is formed in a third metallization layer.