Memory Wordline Drivers With Crossing Row Outputs for Data Integrity
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Solution Overview
Problem
Existing memory devices face issues with electrical coupling between wordlines, leading to data corruption and reduced reliability due to simultaneous activation of adjacent deselected wordlines, particularly in non-volatile memory devices like ferroelectric RAM, where shrinking geometries and faster latency times exacerbate the problem.
Innovation Solution
Implementing non-aligned logical-to-physical addressing for wordlines in memory arrays by using crossover routing, where left and right wordlines of each row are not aligned, reducing the need for a single driver to discharge multiple coupled wordlines simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If wordlines are aligned in memory arrays, then routing and addressing become simpler, but electrical coupling between adjacent wordlines increases causing data corruption
Solution Approach 1:
The patent applies asymmetry by deliberately misaligning wordlines from different patches so that they do not correspond to the same physical location. This asymmetric arrangement breaks the symmetry that would otherwise cause simultaneous coupling of multiple wordlines, thereby improving data integrity while maintaining manageable routing complexity through systematic addressing schemes.
2Quantity of substance
If shrinking geometries are used to increase memory density, then storage capacity increases, but electrical coupling between wordlines worsens leading to more data corruption
Solution Approach 1:
The patent segments the memory array into multiple patches, each with its own set of wordlines. By segmenting the array and independently managing wordline activation in each patch, the system can activate fewer wordlines simultaneously even as overall density increases, thereby maintaining data integrity despite smaller geometries and higher memory density.
3Speed
If faster latency times are implemented, then access speed improves, but the window for electrical coupling interference increases causing more data corruption
Solution Approach 1:
The patent implements preliminary action by pre-charging selected wordlines before the actual read operation begins. This allows the system to prepare the necessary wordlines in advance during the latency period, enabling faster access speeds while controlling the timing of wordline activation to minimize coupling interference and maintain data integrity.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes wordlines connected to rows of memory cells in a memory array. Driver circuitry applies voltages to the wordlines for accessing data stored in the memory cells. A row ordering for the wordlines is implemented with non-aligned logical-to-physical addressing so that wordlines on opposite sides of individual drivers are not physically aligned in the memory array.