Memory Macro Middle Strap Layout for Low-Resistance Power Routing
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Solution Overview
Problem
Existing power routing structures in memory devices, such as SRAM, face challenges with high resistance and degraded supply voltage due to long routing from edge strap areas, especially for high-density memory cells with small active regions, leading to process limitations and blocked backside vias.
Innovation Solution
Incorporating middle strap areas between edge strap areas for power signal routing, which provide shorter paths and reduce resistance, along with feedthrough circuits to connect front and back sides of the memory device, allowing dual-side power routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power signals are routed from edge strap areas to the back side of the memory macro, then chip space is optimized and backside power routing is achieved, but routing length increases causing high resistance and degraded supply voltage
Solution Approach 1:
The patent divides the single edge strap area into multiple strap areas distributed across the memory macro, including both edge strap areas at the periphery and middle strap areas in the interior. This segmentation creates multiple shorter power routing paths from different locations to the back side, reducing the maximum routing length and associated resistance while maintaining backside power routing benefits.
2Productivity
If memory cell active regions are reduced in size to increase density, then production efficiency improves and costs decrease, but backside vias become blocked or improperly formed due to process limitations
Solution Approach 1:
The patent transitions from relying solely on vertical backside vias through small active regions to a distributed strap area architecture that extends power routing into the lateral dimension. By creating middle strap areas within the memory macro interior, the design provides alternative power access paths that do not depend on forming vias through minimized active regions, thus avoiding process limitations while maintaining high density.
3Reliability
If long routing paths are used from edge strap areas to reach the back side, then backside power routing is achieved, but resistance increases and writing voltage (Vmax) degrades
Solution Approach 1:
The patent implements middle strap areas at strategic interior locations within the memory macro to provide locally optimized power access. These middle strap areas create short routing paths for memory cells in the interior regions, ensuring that local power delivery meets the required voltage levels without relying on long paths from edge strap areas. This local quality enhancement directly addresses the writing voltage degradation issue.
Data Source
AI summary
One aspect of the present disclosure pertains to a device. The device includes a memory macro having a frontside and a backside along a vertical direction. The memory macro includes edge strap areas extending lengthwise along a first direction at edges of the memory macro, a memory cell area having a plurality of memory cells, where the memory cell area is disposed between the edge strap areas along a second direction perpendicular to the first direction, and a middle strap area extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, where the middle strap area divides the memory cell area into two memory cell domains. The middle strap area includes a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.