Crossbar Computational Memory Conductance Modulation for Lower Noise
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Solution Overview
Problem
Existing analog memory devices face challenges in achieving optimal conductance modulation to enhance computational precision and reduce energy dissipation, particularly in computational memristive devices like phase change memory (PCM), which suffer from high conductance states leading to noise and imprecision.
Innovation Solution
The method involves determining reduced conductance values for unit cells and optimizing the gate voltage of access transistors to modulate conductance, reducing maximum conductance and improving computational precision by adjusting the gate voltage to operate in the linear or triode region, thereby minimizing noise and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If maximum conductance values are used in unit cells, then storage capacity is improved, but computational precision deteriorates due to noise and energy dissipation
Solution Approach 1:
The patent changes the operating parameter range of unit cells by constraining conductance values to be less than maximum conductance values. This parameter change resolves the contradiction by operating in a reduced conductance range that eliminates noise issues while maintaining sufficient dynamic range for computational precision.
2Quantity of substance
If high conductance states are used, then memory capacity is improved, but energy dissipation increases leading to reduced energy efficiency
Solution Approach 1:
The patent applies parameter changes by operating unit cells in a reduced conductance range (less than maximum conductance values). This change reduces energy dissipation while maintaining adequate conductance dynamic range for computational operations, thereby resolving the energy efficiency contradiction.
3Speed
If access transistor gate voltage is increased, then read capability is improved, but conductance modulation precision deteriorates due to operation outside linear region
Solution Approach 1:
The patent applies dynamics by optimizing the gate voltage of access transistors to operate in the linear region during read operations. This dynamic optimization ensures that the transistor provides consistent current modulation while maintaining conductance modulation precision, resolving the contradiction between read capability and precision.
4Quantity of substance
If maximum conductance values are used, then storage density is improved, but noise increases leading to reduced computational accuracy
Solution Approach 1:
The patent resolves the noise contradiction by changing the operating parameter range to use conductance values less than maximum conductance values. This parameter change eliminates the noise generation mechanism while preserving sufficient conductance dynamic range for accurate computational operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces maximum conductance and enhances computational precision by optimizing gate voltage, leading to improved noise reduction and energy efficiency in analog memory devices.
Implementation Method 1
optimizing the gate voltage of access transistors to modulate conductance, reducing maximum conductance and improving computational precision by adjusting the gate voltage to operate in the linear or triode region
Data Source
AI summary
Systems and methods for modulating conductance of a plurality of unit cells are described. A controller can determine a plurality of conductance values for a plurality of unit cells arranged in a crossbar arrangement. The plurality of unit cells can include non-volatile memory devices. The plurality of conductance values can be less than maximum conductance values of the plurality of unit cells. The controller can determine a read gate voltage for driving a plurality of access transistors to read from connected to the plurality of unit cells under a read operation. The controller can map a plurality of weights to the plurality of conductance values and to the read gate voltage.