DRAM Interleaved Refresh Using Separate Sense Amplifiers
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Solution Overview
Problem
Refresh transactions in dynamic random-access memory (DRAM) interfere with access transactions, limiting sustained bandwidth due to the need for periodic refresh operations that require bitline access.
Innovation Solution
Interleaving refresh transactions into phases that are asynchronous with access transactions, allowing interruptions during specific periods to minimize interference, and optimizing bitline usage through time-shifting and interleaving with access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh transactions are performed periodically to maintain data integrity, then reliability is improved, but access transactions are interfered with and sustained bandwidth deteriorates
Solution Approach 1:
The refresh transaction is segmented into two distinct phases: Phase 1 (sense and store bit value) and Phase 2 (restore value to cell). This segmentation allows Phase 1 to be performed during access periods when bitlines are available, while Phase 2 can be deferred or interrupted without compromising data integrity, thereby reducing interference with access transactions and improving sustained bandwidth while maintaining reliability
Solution Approach 2:
The refresh operation is made dynamic by allowing Phase 2 to be interrupted by access transactions and resumed later. The system dynamically adjusts the timing of refresh operations based on access transaction demands, enabling Phase 2 to be postponed until bitlines are available, thus resolving the conflict between maintaining data integrity and preserving access bandwidth
2Reliability
If refresh transactions use bitline access to sense and restore memory cell values, then data retention is improved, but interference with access transactions increases
Solution Approach 1:
By dividing the refresh transaction into Phase 1 (sense operation during access periods) and Phase 2 (restore operation during idle periods), the invention separates the harmful bitline access interference from the essential data retention function, allowing Phase 1 to complete during access transactions while Phase 2 executes during idle periods without interfering with access operations
Solution Approach 2:
The invention introduces an intermediary mechanism where Phase 1 senses and stores the bit value during access periods without immediately restoring it, using this intermediate storage to decouple the sense operation from the restore operation, thereby eliminating the interference that would occur if both operations were performed simultaneously during access transactions
Data Source
AI summary
A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.