Twin-Bit Memory Cell with a Shared Electrode for Double Density
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Solution Overview
Problem
Existing memory technologies, such as SRAM, DRAM, and RRAM, face challenges in increasing integration density and reducing volume while maintaining non-volatile memory functionality.
Innovation Solution
Integration of a nanotube memory cell with a resistive memory cell, utilizing a tantalum oxide and tantalum pentoxide resistive layer, forming a twin-bit memory cell that shares a common electrode, thereby doubling memory density and reducing volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing memory technologies (SRAM, DRAM, RRAM) are used, then non-volatile memory functionality is maintained, but integration density and volume reduction are limited
Solution Approach 1:
The patent combines nanotube memory cell and resistive memory cell into a single integrated structure that shares a common electrode (middle electrode). This merging of two different memory technologies into one hybrid cell achieves higher integration density while reducing the volume occupied per memory unit, as the shared electrode eliminates redundant structures.
Solution Approach 2:
The middle electrode serves dual functionality as both the top electrode for the nanotube memory part and the bottom electrode for the resistive memory part. This multi-functional design allows the same structural element to participate in two different memory mechanisms, improving space utilization and integration density.
2Productivity
If nanotube memory cell and resistive memory cell are integrated, then memory density is doubled, but device structure becomes more complex
Solution Approach 1:
By merging nanotube and resistive memory cells into a single integrated structure with shared electrodes, the patent achieves doubled memory density while actually reducing overall structural complexity compared to implementing two separate memory cells. The common middle electrode consolidates what would otherwise be separate components.
Solution Approach 2:
The patent implements a stacked three-dimensional architecture where nanotube and resistive memory parts are arranged vertically with shared electrodes. This dimensional arrangement allows both memory types to coexist in the same footprint area, doubling density without proportionally increasing planar complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated memory cell achieves double memory density, smaller volume, and lower processing costs by combining nanotube and resistive memory components, with distinct states achieved through varying voltage applications.
Implementation Method 1
the carbon nanotubes attract or repel each other while signal writing. Each physical state (attracting or repelling) corresponds to a circuit state. The repulsion state is an open circuit state, while the attraction state is a closed state in which a rectifying junction is formed.
Implementation Method 2
the middle electrode, the resistive layer and the top electrode constituting a resistive memory part
Data Source
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Figure 5~6
AI summary
A memory cell is disclosed which includes a first conductive line (132) disposed over a substrate (110), a lower electrode (142), a carbon nano-tube (CNT) layer (144), a middle electrode (146), a resistive switching layer (148), preferably of Ta 2O 5 stacked on TaO x , and a top electrode (149) successively disposed on the first conductive line, and a second conductive line (192) disposed over the top electrode. The lower electrode, the CNT layer, and the middle electrode constitute a first memory part whereas the middle electrode, the resistive switching layer, and the top electrode constitute a second memory part, thereby forming a twin-bit memory cell.