Memory Clock Circuit Separation for High-Speed DFT Operation
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Solution Overview
Problem
Existing memory devices face inefficiencies in DFT operations due to significant timing penalties and speed limitations when using external or SOC clocks for internal clock generation, which disable read and write signals during DFT operations.
Innovation Solution
A memory device with independent clock generators for local and global clock signals, allowing separate tuning of power, performance, and area for DFT and mission modes, enabling independent clock generation without affecting normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external or SOC clocks are used for internal clock generation during DFT operations, then the memory device can perform DFT testing, but significant timing penalties occur and DFT operation speed is limited
Solution Approach 1:
The patent divides the clock generation function into two separate clock generators: one dedicated to mission mode operations and another dedicated to DFT mode operations. This segmentation allows each clock generator to be optimized independently, enabling high-speed DFT operations without being constrained by the timing requirements of mission mode clocks.
Solution Approach 2:
The patent introduces an intermediary mechanism (the second clock generator) that provides dedicated clock signals for DFT operations. This intermediary clock generator acts as a mediator between the external/SOC clock and the DFT testing operations, eliminating the timing penalties that would otherwise be imposed by using the mission mode clock for DFT operations.
2Reliability
If read and write signals are disabled during DFT operations using external/SOC clocks, then DFT testing can be performed, but mission mode operations are interrupted and overall system productivity decreases
Solution Approach 1:
The patent segments the operational modes by providing separate clock generators for mission mode and DFT mode. This allows DFT operations to be performed with dedicated clock signals while mission mode operations continue uninterrupted with their own clock signals, thereby maintaining system productivity during testing.
Solution Approach 2:
The patent implements dynamic clock signal selection through control logic that can switch between or independently activate clock signals for different operational modes. This dynamic approach enables the system to maintain optimal performance characteristics for both mission mode and DFT mode without requiring signal disabling.
3Device complexity
If a single clock generator is used for both mission mode and DFT mode, then device complexity is reduced, but independent tuning of power, performance, and area for each mode is not possible
Solution Approach 1:
The patent applies segmentation by creating two separate clock generators, each dedicated to a specific operational mode. This segmentation enables independent tuning of power, performance, and area parameters for each mode without affecting the other, achieving optimal adaptation for both mission mode and DFT mode operations.
Solution Approach 2:
While introducing separate clock generators, the patent maintains a universal control structure that manages both clock generators through a unified interface. This allows the system to benefit from independent optimization while preserving a degree of structural unity and control simplicity.
Data Source
AI summary
A memory device includes a plurality of memory cells arranged in an array, a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells, a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface, and one or more logic gates connected to at least one of the first clock generator or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently.