Per-Row Activation Counters with ECC for DRAM Row Hammer Mitigation
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) cells are susceptible to data loss due to charge leakage during standby mode and face data corruption from the 'row hammer' effect, where frequently accessed rows cause adjacent rows to lose data, which existing refresh mechanisms struggle to mitigate effectively.
Innovation Solution
Incorporating additional counter cells per row to track activations, with error correction code (ECC) protection to ensure accurate counting, and implementing threshold-based row hammer mitigation strategies to refresh vulnerable rows, along with dynamic threshold adjustments and ECC processing to minimize performance impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional counter cells per row are added to track activations, then row hammer detection capability is improved, but memory chip area and complexity increase
Solution Approach 1:
The counter cells are segmented and distributed across different rows rather than using a centralized counter. Each row has its own counter cells located within or near that row's storage cells, allowing localized tracking of activation counts without requiring a separate centralized counter structure.
Solution Approach 2:
The counter cells are merged with the existing memory array structure. Instead of adding completely separate counter circuits, the counter functionality is integrated into the memory cell structure itself, sharing physical space and circuit resources with the storage cells.
2Measurement precision
If ECC protection is added to counter cells, then counting accuracy is improved, but processing time and complexity increase
Solution Approach 1:
ECC protection bits are pre-calculated and stored alongside the counter values. When a row activation occurs, the ECC bits are already in place and can be quickly verified without requiring time-consuming recalculation, thus maintaining counting accuracy while minimizing processing time overhead.
Solution Approach 2:
The ECC protection mechanism uses simplified copy-based verification rather than complex recalculation. The ECC bits are copied and verified against the current counter state, providing accurate error detection with minimal processing overhead compared to full recalculation methods.
3Reliability
If frequent refreshes are performed to protect against row hammer, then data integrity is improved, but memory performance and throughput deteriorate
Solution Approach 1:
The system uses feedback from the counter cells to dynamically determine when refresh operations are needed. Instead of performing periodic refreshes regardless of actual need, the counter values provide feedback about row activation frequencies, allowing the system to refresh only those rows that have exceeded activation thresholds, thus maintaining data integrity while minimizing unnecessary refresh operations.
Solution Approach 2:
The refresh strategy transitions from static periodic refreshing to dynamic conditional refreshing. The system continuously monitors counter values and adjusts refresh timing based on actual row activation patterns, refreshing rows dynamically when thresholds are exceeded rather than following a fixed schedule, thereby optimizing both reliability and performance.
Data Source
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AI summary
A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.