Embedded DRAM Canary Cells for Leakage-Aware Refresh Control
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Solution Overview
Problem
Embedded DRAMs face challenges in managing refresh operations due to data loss from leakage, leading to increased latency and power consumption, as the refresh frequency is typically set by the leakiest cell, which is inefficient.
Innovation Solution
Implementing canary cells that are deliberately designed to be more susceptible to leakage than main cells, allowing for the identification of impending failures and enabling a lower refresh rate by setting the refresh frequency based on the canary cells' failures, which can be corrected by error correction code (ECC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh frequency is set by the leakiest cell to prevent data loss, then data integrity is maintained, but power consumption and latency increase
Solution Approach 1:
The patent segments the DRAM cells into two distinct groups: canary cells designed with higher leakage characteristics and main storage cells with normal leakage characteristics. This segmentation allows the system to monitor leakage behavior separately from storage operations, enabling optimized refresh strategies that don't require refreshing all cells at the conservative rate dictated by the leakiest cell.
Solution Approach 2:
The canary cells serve as intermediary elements that mediate between the need for data integrity and power consumption optimization. By monitoring canary cell failures rather than directly monitoring all main storage cells, the system can determine appropriate refresh rates for the main array, reducing unnecessary refresh operations while maintaining data integrity.
2Reliability
If refresh frequency is set by the leakiest cell to prevent data loss, then data integrity is maintained, but latency increases
Solution Approach 1:
The patent segments the DRAM cells into two distinct groups: canary cells designed with higher leakage characteristics and main storage cells with normal leakage characteristics. This segmentation allows the system to monitor leakage behavior separately from storage operations, enabling optimized refresh strategies that don't require refreshing all cells at the conservative rate dictated by the leakiest cell.
Solution Approach 2:
The canary cells serve as intermediary elements that mediate between the need for data integrity and latency reduction. By monitoring canary cell failures rather than directly monitoring all main storage cells, the system can determine appropriate refresh rates for the main array, reducing unnecessary refresh operations and associated latency while maintaining data integrity.
3Productivity
If canary cells are designed to be more susceptible to leakage, then refresh rate can be optimized, but device complexity increases
Solution Approach 1:
The patent applies local quality by giving canary cells distinct characteristics (higher leakage susceptibility) compared to main storage cells. This localized differentiation in cell properties allows the system to extract leakage information without requiring complex monitoring circuitry across the entire array, as the canary cells inherently provide the needed information through their designed behavior.
Solution Approach 2:
The patent changes physical parameters of canary cells (transistor dimensions, voltage levels) to increase leakage susceptibility. By modifying these parameters in specific cells, the system creates natural indicators of leakage behavior that simplify the overall refresh management logic, as canary failures directly indicate when main array cells are approaching failure thresholds.
Data Source
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AI summary
A dynamic random access memory (DRAM) includes a plurality of main bit cells, a first set of write bit lines, a first set of write word lines, a plurality of canary cells, a second set of write bit lines, and a second set of write word lines. Each main bit cell has a capacitive storage element and is coupled to a corresponding write bit line of the first set of bit lines and a corresponding write word line of the first set of write word lines. The plurality of canary cells are configured to be more susceptible to leakage currents as compared the plurality of main bit cells. Each canary cell has a capacitive storage element and is coupled to a corresponding write bit line of the second set of bit lines and a corresponding write word line of the second set of write word lines.