Staggered Vertical Transistors for Dense Memory Cell Layouts
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased fabrication complexity and cost as feature sizes approach a lower limit, limiting memory density and efficiency.
Innovation Solution
Implementing vertical transistors with a semiconductor body extending in a first direction and a bit line perpendicular to it, allowing for a staggered layout and multiple stacked storage units, reducing transistor area and simplifying interconnect structures, and using face-to-face bonding of memory cell arrays and peripheral circuits to reduce chip size and fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) memory cell architecture. The vertical transistor structure extends the channel in the vertical direction rather than laterally, enabling memory density improvement without proportionally increasing fabrication complexity. This dimensional change allows stacking multiple storage nodes vertically, effectively increasing storage capacity while maintaining manageable process complexity.
2Quantity of substance
If feature sizes of memory cells approach a lower limit, then memory density approaches an upper limit, but planar process techniques become challenging and costly
Solution Approach 1:
By moving to vertical transistors, the patent avoids further lateral scaling of feature sizes. Instead of making transistors smaller in the plane, the channel length is extended vertically, allowing memory density to increase without requiring increasingly complex planar lithography and fabrication techniques.
Solution Approach 2:
The vertical transistor structure enables nested arrangement of storage nodes along the vertical channel, with multiple storage nodes stacked above each other. This nesting approach increases the number of storage elements per transistor without requiring proportionally smaller feature sizes, thereby improving manufacturability while increasing density.
3Area of moving object
If vertical transistors with staggered layout are implemented, then transistor area is reduced, but device structure complexity increases
Solution Approach 1:
The patent employs asymmetric staggered layout where source and drain regions are positioned at different vertical heights. This asymmetric arrangement reduces the planar footprint of the transistor by utilizing the vertical dimension for differentiation, thereby reducing transistor area while the modular nature of the staggered structure keeps fabrication complexity manageable.
4Area of stationary object
If face-to-face bonding of memory cell arrays and peripheral circuits is used, then chip size is reduced, but fabrication process complexity increases
Solution Approach 1:
The patent employs face-to-face bonding to merge memory cell arrays and peripheral circuits onto a single chip substrate. This consolidation reduces the overall chip size by eliminating the need for separate packages or larger substrate areas, while the bonding process itself, though complex, is a established technology that manages fabrication complexity.
Solution Approach 2:
The patent segments the memory device into distinct functional modules (memory cell arrays and peripheral circuits) that are fabricated separately and then bonded together face-to-face. This segmentation allows independent optimization of each module and simplifies the overall fabrication workflow despite the added bonding step, as each module can be processed using standard techniques before integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory cell density, reduces fabrication complexity, and improves yield by minimizing transistor area and coupling capacitance while suppressing the floating body effect, enabling high-speed data transfer with reduced power consumption.
Implementation Method 1
The semiconductor body includes a doped source, a doped drain, and a channel portion
Data Source
AI summary
In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.