Multi-Stage Memory Clock Partitioning for Lower RC Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory architectures face challenges in reducing access time and power consumption due to increased resistance and capacitance, particularly in lower technology nodes, leading to significant RC delays and toggle power, which are exacerbated by the use of buffers and two-stage clock partitioning schemes.
Innovation Solution
A memory architecture that partitions the internal clock into multiple stages, specifically three segments, distributing gate and metal capacitance loads to reduce RC delay and power consumption while optimizing silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If buffers are inserted into clock paths to reduce RC delay, then access time is improved, but silicon area and toggle power increase
Solution Approach 1:
The clock distribution network is divided into multiple stages (first stage driven by metal load, second stage driven by gate load) with buffers strategically placed at boundaries. This segmentation allows each stage to be optimized independently, reducing overall RC delay while minimizing the number of buffers required, thus lowering toggle power compared to a single-stage approach.
Solution Approach 2:
Different buffer insertion strategies are applied to different regions of the clock network based on local RC characteristics. Buffers are placed where they provide maximum benefit in reducing access time while considering the local capacitance and resistance values, optimizing the trade-off between speed and power consumption.
2Loss of time
If more buffers are added to reduce RC delay, then access time is improved, but silicon area increases
Solution Approach 1:
The clock network is segmented into multiple stages with buffers placed only at critical boundaries where RC delay is most significant. This reduces the total number of buffers required compared to uniform buffer insertion, thereby reducing silicon area while still achieving improved access time through optimized clock distribution.
3Speed
If gate oxide thickness is reduced to improve transistor performance, then switching speed is improved, but capacitance increases leading to larger toggle power
Solution Approach 1:
The clock distribution is segmented into stages that account for the increased gate capacitance caused by reduced oxide thickness. By distributing the capacitive load across multiple stages with appropriately sized buffers, the system maintains switching speed while managing toggle power through optimized buffer sizing and placement.
Solution Approach 2:
Buffer sizes and placement are adjusted based on the changed capacitance parameters resulting from reduced gate oxide thickness. The clock network parameters (buffer dimensions, spacing, and staging) are modified to compensate for the increased capacitance, maintaining optimal switching performance while controlling power consumption.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory (300) comprises a multi stage clock-partitioning circuit, and at least one upper bitcell memory array (350, 352) and at least one lower bitcell memory array (354, 356). An input is configured to receive an external clock signal. A first stage (210) of the multi stage clock-partitioning circuit is configured to receive the external clock signal and generate a first internal clock signal and provide the first internal clock signal to the bitcell memory arrays. A second stage (220) of the multi stage clock-partitioning circuit is configured to receive the first internal clock signal and generate a second internal clock signal. A third stage (230) of the multi stage clock-partitioning circuit is configured to receive the second internal clock signal and generate a third word line generated clock signal and provide the third internal clock signal to the at least upper and lower bitcell memory arrays.