Non-Interleaving N-Well/P-Well Pickup Layout for Latch-Up Control

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Solution Overview

Problem

The scaling down of P-well and N-well pickup regions in semiconductor devices leads to implant aperture effects and inter-well implant dose compensation, causing issues such as latch-up, device performance degradation, and failures, particularly in 7-nanometer technology nodes and beyond.

Innovation Solution

Reconfigure small and interleaving N-well and P-well pickup regions into larger continuous regions, reducing N/P boundaries and minimizing implant aperture effects, thereby improving device yield and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If P-well and N-well pickup regions are scaled down to increase device density, then functional density increases, but implant aperture effects and inter-well implant dose compensation occur causing latch-up and device failures

Engineering Contradiction:
Improvedevice densityVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The pickup regions are segmented into separate N-well and P-well regions that are non-interleaved, with each type grouped together. This segmentation eliminates the inter-well implant dose compensation that occurs in interleaved structures, preventing latch-up while maintaining scaled-down dimensions for high density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

All N-well pickup regions are merged into continuous N-well regions, and all P-well pickup regions are merged into continuous P-well regions. This merging eliminates the boundaries between alternating N/P wells, preventing implant dose compensation at interfaces while achieving high device density through compact layout.

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If small interleaved N-well and P-well pickup regions are used, then chip area is reduced, but contact resistance increases and latch-up problems occur

Engineering Contradiction:
Improvechip areaVSAvoiddevice reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The structure is segmented into distinct N-well and P-well regions rather than interleaved patterns. This segmentation reduces the total perimeter length and number of N/P interfaces, lowering contact resistance while preventing latch-up through elimination of dose compensation at boundaries.

Inventive Principle:
Principle #1Segmentation

3Productivity

If scaling down continues to increase production efficiency, then manufacturing cost decreases, but implant aperture effects cause device failures

Engineering Contradiction:
Improveproduction efficiencyVSAvoidimplant precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

By merging all N-well regions into continuous blocks and all P-well regions into continuous blocks, the total number of implant boundaries is minimized. This merging reduces the cumulative aperture effects at multiple interfaces, improving implant precision while maintaining scaled-down dimensions for high production efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces contact resistance and the likelihood of latch-up problems, enhancing device performance and reliability by eliminating or reducing inter-well implant dose compensation and implant aperture effects.

Implementation Method 1

The doping process may include ion implantation

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS12464697B2Non-interleaving N-well and P-well pickup region design for IC devices
Publication Date: 2025.11.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12464697B2 patent drawing
  • US12464697B2 patent drawing
  • US12464697B2 patent drawing

AI summary

A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N-well and a plurality of P-type transistors formed over the first portion of the N-well. The first region extends in a first direction. The second region includes a first portion of a P-well and a plurality of N-type transistors formed over the first portion of the P-well. The second region extends in the first direction. The third region includes a second portion of the P-well. The fourth region includes a second portion of the N-well. The first region and the second region are disposed between the third region and the fourth region.