3D Memory Cell Layout With Side Pad Regions for Higher Density
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in integration due to the area occupied by unit memory cells, hindering the development of high-capacity devices as electronic products become more compact and multi-functional.
Innovation Solution
A three-dimensional semiconductor memory device is proposed, where memory cells are stacked vertically, with word lines and bit lines arranged in specific directions, and connected to sub-word line drivers through word line contacts, allowing for increased integration by reducing the area occupied by pad regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally to increase integration, then the degree of integration is improved, but the area occupied by unit memory cells limits further integration
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple memory cell layers vertically on the substrate. This dimensional change allows memory cells to be arranged in multiple levels (first stacked region, second stacked region, etc.), significantly increasing the number of memory cells per unit area and overcoming the integration limits of planar designs.
2Quantity of substance
If pad regions are reduced to increase integration, then the number of memory cells per unit area is improved, but the connection to external circuits becomes more complex
Solution Approach 1:
The patent reduces pad region area by relocating pad regions to vertical sidewalls of stacked regions rather than occupying large horizontal areas. Word line contacts extend vertically to connect word lines from multiple stacked regions to sub-word line drivers positioned on the sidewalls, enabling compact pad region design while maintaining external circuit connectivity.
Solution Approach 2:
The patent implements nested structures where word line contacts are embedded within insulating structures that extend from the substrate upward. Multiple word line contacts can be vertically stacked and interconnected, allowing compact routing of signals from multiple memory cell layers to external circuits through shared vertical pathways.
3Quantity of substance
If multiple stacked regions are arranged horizontally to increase capacity, then the memory capacity is improved, but the horizontal area occupied increases
Solution Approach 1:
The patent arranges multiple stacked regions (first stacked region, second stacked region, etc.) in a vertical configuration rather than spreading them horizontally. Memory cells are stacked in multiple layers within each stacked region, and multiple stacked regions are positioned close together with shared pad regions on sidewalls, maximizing memory capacity within a compact horizontal footprint.
Data Source
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AI summary
A semiconductor memory device (1) including a substrate including a first stacked region, a second stacked region, and a pad region, the pad region being between the first stacked region and the second stacked region in a first horizontal direction (X), a plurality of word lines (WL) extending from the pad region toward each of the first stacked region and the second stacked region in the first horizontal direction (X) and spaced apart from each other in a vertical direction (Z), a plurality of bit lines (BL) extending in the vertical direction (Z) and spaced apart from each other in the first horizontal direction (X) in each of the first stacked region and the second stacked region, and a plurality of memory cells (MC) interposed between the plurality of word lines (WL) and the plurality of bit lines (BL) in each of the first and second stacked regions may be provided.