3D Nonvolatile Memory With Common Source Contact
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Solution Overview
Problem
The existing two-dimensional nonvolatile memory devices have reached integration limits, necessitating the development of three-dimensional nonvolatile memory devices with vertically stacked memory cells, which require improved structural stability and operational reliability.
Innovation Solution
A semiconductor device with hole source patterns, electron source patterns, and channel layers, where the channel layers are in common contact with adjacent hole and electron source patterns, and a stack structure formed by alternately stacking conductive and insulating layers, with barrier patterns to prevent impurity mixing and ensure electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional nonvolatile memory devices are used, then manufacturing process is simple, but integration degree reaches upper limit
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking, where memory cells are arranged along the vertical direction (third direction) rather than only in the planar direction. This dimensional change enables significantly higher integration density while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The patent implements nested structures where channel layers, memory layers, and interlayer insulating layers are stacked vertically to form compact three-dimensional memory cells. Multiple functional layers are nested within each other along the vertical axis, achieving high integration without increasing planar footprint.
2Quantity of substance
If three-dimensional nonvolatile memory devices with vertically stacked memory cells are developed, then integration degree increases, but structural stability deteriorates
Solution Approach 1:
The patent divides the vertical stack into discrete functional segments including channel layers, memory layers, and interlayer insulating layers. Each layer is independently formed and controlled, allowing precise management of material properties and interfaces to ensure structural stability in the three-dimensional configuration.
Solution Approach 2:
The patent employs composite material structures combining different functional layers (conductive channel layers, insulating interlayer insulating layers, and memory layers) with complementary properties. This multi-material approach enhances overall structural stability while enabling the three-dimensional vertical stacking architecture.
3Quantity of substance
If three-dimensional nonvolatile memory devices with vertically stacked memory cells are developed, then integration degree increases, but operational reliability deteriorates
Solution Approach 1:
The patent introduces interlayer insulating layers as intermediary structures between adjacent memory cells in the vertical stack. These insulating layers provide electrical isolation and prevent interference between neighboring cells, ensuring reliable operation of each memory cell independently within the three-dimensional structure.
Solution Approach 2:
The patent assigns specific functional properties to different regions of the vertical stack, with channel layers providing conductive paths, memory layers providing data storage functionality, and interlayer insulating layers providing electrical isolation. This localized functional differentiation ensures reliable operation of each component in its designated region.
4Reliability
If channel layers are in common contact with adjacent hole source patterns and electron source patterns, then manufacturing complexity increases, but device characteristics improve
Solution Approach 1:
The patent merges the formation of hole source patterns and electron source patterns into a single integrated structure where channel layers are in common contact with both types of source patterns. This unified configuration simplifies the manufacturing process by reducing the number of separate patterning steps while maintaining improved device characteristics.
Data Source
AI summary
A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.