3D Semiconductor Memory Device With Configurable Interconnects
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor fabrication, particularly for custom Integrated Circuits, limits the development of cost-effective and flexible solutions for custom products with varying logic, memory, and I/O requirements, as existing methods require multiple expensive mask sets for each product variation.
Innovation Solution
The development of a 3D IC device fabrication method using Through-Silicon Via (TSV) technology and antifuse configurable interconnect circuits, allowing for the construction of configurable logic, memory, and I/O dies with reduced mask costs by using thin film transistors for programming circuits and overlaying transistors above or below antifuse layers, enabling modular and flexible system construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple custom mask sets are used for each product variation, then product customization capability is improved, but mask set cost increases exponentially
Solution Approach 1:
The patent implements a universal mask set that can fabricate multiple different custom IC products by utilizing configurable logic arrays and programmable interconnect structures. A single master mask set defines the basic device architecture, while product-specific functionality is achieved through programming and configuration rather than requiring separate custom masks for each product variation.
Solution Approach 2:
The IC structure is divided into configurable logic arrays, programmable interconnect layers, and fixed functional blocks. This segmentation allows different portions of the device to be customized through programming rather than requiring custom masks, enabling multiple products from a single mask set while maintaining manufacturing efficiency.
2Manufacturing precision
If dedicated mask sets are created for each custom product, then manufacturing precision for specific designs is improved, but device complexity and development time increase
Solution Approach 1:
The patent pre-defines the basic device architecture, transistor structures, and interconnect frameworks using a universal mask set before product customization. This preliminary structuring ensures manufacturing precision is maintained while avoiding the need to create and manage multiple complete mask sets for different products.
Solution Approach 2:
Product customization is achieved by changing programmable parameters and configuration settings rather than changing physical mask patterns. This allows different products to be manufactured with the same mask set by adjusting device programming and interconnect configuration, maintaining precision while reducing complexity.
3Reliability
If custom mask sets are used for small volume custom products, then product performance is improved, but cost-effectiveness deteriorates
Solution Approach 1:
The universal mask set enables small volume custom products to be manufactured with the same equipment and processes used for high-volume production, achieving cost economies of scale while maintaining product performance through programmable customization rather than custom tooling.
4Adaptability or versatility
If multiple master slices are created to cover range of logic, memory and I/O options, then adaptability is improved, but mask set cost and complexity increase
Solution Approach 1:
The patent implements dynamically reconfigurable logic arrays and interconnect structures that can be programmed to provide different logic, memory, and I/O configurations. This dynamic adaptability replaces the need for multiple static master slices, allowing a single mask set to support a wide range of product configurations through programming rather than physical reconfiguration.
Data Source
AI summary
A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.