Transistor TRIZ Cases
- Polysilicon FinFET 1T DRAM Cell Hole Trapping
A polysilicon FinFET 1T DRAM cell traps accumulated holes to improve retention time.
- SiC Semiconductor Device with P-Type Drift Layer
A silicon carbide semiconductor device uses a p-type drift layer to control surface potential and regulate current flow between source and drain regions.
- Atomic Layer Deposition for High-k Dielectric Density
Atomic layer deposition creates high-k dielectric layers via sequential precursor cycles, resolving leakage issues at 40 nm and 28 nm nodes.
- ESD Protection Circuit with RC-Gated SCR for Holding Voltage Control
A gate-coupled capacitor triggers a silicon controlled rectifier, raising holding voltage to prevent electrical overstress without disrupting normal operation.
- Plasma Interface Engineering for Resistive Memory Metal Oxide Films
Plasma processing engineers metal oxide interfaces to enhance electrical contact and control resistivity in memory devices.
- SiC BJT Conductivity Modulation via Intermediate Region Doping
Adjusting the doping level of an intermediate region between the base and contact reduces forward voltage drop while maintaining switching speed.
- FinFET Device With Segmented SiGeO and Ge Layers
Segmented SiGeO and Ge layers in a FinFET structure reduce epitaxial defects while enhancing electron mobility.
- Semiconductor Grid Gate Structure Reducing Parasitic Capacitance
A semiconductor grid gate structure with stripe-shaped edge portions and wider node portions connects multiple transistor sections to optimize active area.
- Short-to-Ground Protection Circuit for Pass FET
Sense circuit detects voltage drop magnitude and change rate at pass FET output, inducing control current to turn off the device before damage occurs.
- Heterostructured Cathodes Reduce Electrical Disturb in Thyristor Memory
Heterostructured cathodes reduce minority carrier lifetime to minimize electrical disturb effects between adjacent thyristor memory cells.
- Monolithic Compound Semiconductor ESD Protection Structure
Replaces series diodes with a monolithic thyristor pnpn junction to reduce die area while increasing trigger voltage for electrostatic discharge protection.
- Active Matrix Substrate Using Transparent Conductive Intermediary
A transparent conductive layer connects gate and source metal layers in an active matrix substrate.
- High Voltage CMOS Triple Gate Oxide Transistor
A high voltage MOS transistor uses a closed loop gate structure to operate at 30 volts.
- Stacked Device Isolation Structure for Compressive Stress Engineering
Graded compressive stress in a stacked device isolation structure improves carrier mobility while mitigating short channel effects.
- Methanol Plasma Sputter Etching for Copper Interconnect Liner Coverage
Sputter etching conductive metal with methanol plasma forms precise copper lines in multi-layer integrated circuit structures.
- Semiconductor Structure Metallide Contact Resistance
Different metallides on n-type and p-type regions reduce contact resistance by optimizing barrier heights.
- Biased ESD Circuit Reducing Capacitance via Negative Bulk Bias
Applying negative bulk bias reduces drain-to-source capacitance in the ESD structure while maintaining clamping reliability.
- Shared Gate Transfer Transistors for Solid-State Imaging Power Reduction
A solid-state imaging pixel uses shared gate electrodes to control multiple transfer transistors simultaneously.
- Graphene NMOS Transistor Using NO2 Adsorption for Digital Logic
Nitrogen dioxide adsorption induces electron depletion in graphene channels, resolving the missing bandgap bottleneck while preserving high electron mobility.
- Semiconductor Contact Isolation via Etch Control Layers
Isolated contact filling portions surrounded by etch control layers enable precise interconnection patterning in semiconductor manufacturing.
- Antifuse Memory Cell Programming Path Bypasses Read Transistor
A nonvolatile memory cell design routes programming current through an antifuse component to protect the read transistor gate dielectric from high voltage stress.