ESD Protection Circuit with RC-Gated SCR for Holding Voltage Control
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Solution Overview
Problem
Existing ESD protect circuits in integrated circuits often have a low holding voltage, leading to frequent electrical overstress events, and fail to protect internal circuits effectively without disrupting normal operation.
Innovation Solution
An ESD protection device utilizing a Silicon Controlled Rectifier (SCR) that can be triggered rapidly, with adjustable breakdown speed, and reduced anode-cathode distance to save layout area, featuring a substrate with doped regions and a gate structure that allows for controlled ESD voltage application via a RC circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the holding voltage of the discharge path is increased to prevent electrical overstress events, then the protection effectiveness is improved, but the normal operation of internal circuits may be disrupted
Solution Approach 1:
The patent employs dynamic voltage control through a capacitor-connected gate that responds to ESD events. The holding voltage is not fixed but dynamically adjusted based on the presence of ESD disturbances, allowing the circuit to maintain high protection voltage during ESD events while returning to normal operating voltage otherwise
Solution Approach 2:
The patent changes the voltage parameter of the discharge path dynamically. By controlling the gate voltage through a capacitor, the holding voltage transitions between two states: a higher voltage state during ESD events for effective protection, and a lower voltage state during normal operation to avoid disrupting internal circuits
2Area of stationary object
If the distance between anode and cathode is reduced to save layout area, then the device area is reduced, but the turn-on speed may be adversely affected
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor connected to the gate before the ESD event occurs. This preliminary energy storage in the capacitor enables rapid gate voltage adjustment and quick SCR triggering, achieving fast turn-on speed without requiring a large anode-cathode distance
Solution Approach 2:
The patent introduces a capacitor as an intermediary element between the ESD voltage source and the SCR gate. This capacitor mediates the energy transfer, enabling rapid voltage application to the gate for quick SCR activation, thereby achieving fast turn-on speed with compact layout
3Speed
If the breakdown speed of the transistor is increased for rapid ESD response, then the ESD protection response time is reduced, but the control precision over breakdown timing may be reduced
Solution Approach 1:
The patent implements feedback control through the RC circuit connected to the gate. The resistor and capacitor create a time constant that provides controlled charging/discharging behavior, enabling precise control over the breakdown timing while maintaining rapid response capability. The feedback mechanism ensures that the breakdown occurs at the optimal moment for ESD protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables rapid triggering of the SCR during ESD events, reduces layout area requirements, and adjusts breakdown speed without affecting normal circuit operation, effectively protecting internal circuits from electrical overstress.
Implementation Method 1
the gate is coupled to a capacitor and a resistor... the gate is disposed over the substrate between the first doped region and the second doped region... When an ESD voltage is applied to the bonding pad, the ESD voltage is coupled to the gate
Implementation Method 2
a transistor that includes a first doped region of the second conductivity type located in the substrate and extending into the well, a second doped region of the first conductivity type located in the substrate and neighboring to the first doped region... The third doped region is located between the second doped region and the fourth doped region
Data Source
AI summary
An ESD protection device is described, including a substrate of a first conductivity, a well of a second conductivity, a transistor including a first doped region of the second conductivity located in the substrate and extending into the well, a second doped region of the first conductivity and a gate over the substrate between the two doped regions, a third doped region of the second conductivity and a fourth doped region of the first conductivity disposed in the substrate in sequence from an outer side of the second doped region and coupled to ground, and a fifth doped region of the first conductivity and a sixth doped region of the second conductivity disposed in the well in sequence from an outer side of the first doped region and coupled to a bonding pad. When an ESD voltage is applied to the bonding pad, it is coupled to the gate.