Heterostructured Cathodes Reduce Electrical Disturb in Thyristor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM cell technologies face challenges in scaling due to high capacitance and low transistor leakage, with alternative designs like floating body DRAM and pnpn thyristor cells experiencing data retention issues and process complexity, particularly at smaller dimensions.
Innovation Solution
Vertical thyristors arranged in cross-point arrays with a cathode line made from materials that reduce minority carrier lifetime, such as metal silicide, to minimize electrical disturb effects and improve performance, using techniques like trench isolation and potential wells to confine or divert minority carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM cell scaling is pursued, then bit density increases, but capacitance maintenance and leakage control become increasingly difficult
Solution Approach 1:
The patent transitions from conventional 1T1C DRAM parameters to thyristor-based memory parameters, changing the fundamental operating mechanism from capacitor charge storage to thyristor switching states. This parameter change enables scaling while maintaining reliability through the thyristor's inherent latch-up characteristic that provides stable binary states without requiring large capacitance values.
Solution Approach 2:
The patent replaces the mechanical capacitor-based charge storage system with a semiconductor-based thyristor switching system. This substitution eliminates the need for physical capacitor structures and their associated leakage and capacitance maintenance issues, while enabling higher density through the thyristor's compact structure and ability to be arranged in cross-point arrays.
2Productivity
If alternative DRAM cell designs like floating body DRAM are used, then scaling challenges are addressed, but data retention issues persist particularly at scaled dimensions
Solution Approach 1:
The patent introduces the thyristor as an intermediary device between the scaling requirement and data retention requirement. The thyristor's four-layer pnpn structure with regenerative feedback mechanism acts as a mediator that provides stable data retention through its latch-up characteristic, while its compact vertical structure enables scaling. The thyristor replaces the floating body transistor's unreliable charge storage with a more reliable switching mechanism.
3Ease of operation
If pnpn thyristor cells operated in breakdown regime are used, then data writing is achieved, but process control challenges and power consumption increase
Solution Approach 1:
The patent changes the operating parameters of the thyristor from breakdown regime operation to forward active region operation. By applying write currents that forward-bias the p-n junctions rather than relying on reverse breakdown, the patent reduces power consumption and simplifies process control while maintaining the ability to write data through controlled switching between ON and OFF states.
4Productivity
If vertical thyristors are arranged in cross-point arrays with shared cathode lines, then cell density increases, but electrical disturb effects between adjacent cells occur
Solution Approach 1:
The patent extracts and removes minority carriers from the shared cathode line through recombination mechanisms. By introducing recombination centers or using material properties that promote carrier recombination in the cathode region, the patent prevents minority carriers generated in one cell from diffusing into adjacent cells and causing electrical disturb effects, while maintaining the high-density cross-point array structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a compact, reliable, and easily integratable memory cell design with reduced disturb effects, allowing for shallower trench isolations and lower fabrication complexity, thereby enhancing memory cell density and performance.
Implementation Method 1
a cathode line connecting a first thyristor and second thyristor within a cross-point memory array is composed of a material that reduces a minority carrier lifetime within the cathode to reduce electrical disturb effects between the first thyristor and the second thyristor
Implementation Method 2
a potential well may be formed within a cathode line connecting a first thyristor and a second thyristor within a cross-point memory array to confine minority carriers in order to reduce electrical disturb effects between the first thyristor and the second thyristor
Data Source
AI summary
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.