Stacked Device Isolation Structure for Compressive Stress Engineering
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Solution Overview
Problem
The reduction in transistor size to increase operating speed leads to the Short Channel Effect, which decreases breakdown voltage, increases junction capacitance, and instability, making it difficult to improve carrier mobility effectively using conventional stress application methods and materials like silicon germanium source/drain regions or Silicon-on-Insulator substrates.
Innovation Solution
A modified device isolation structure with a stacked structure of upper and lower device isolation structures, where the upper structure has greater compressive stress than the lower one, applied differently to PMOS and NMOS regions to enhance carrier mobility by adjusting stress levels specifically for each type of transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If device size is reduced to increase operating speed, then operating speed is improved, but Short Channel Effect worsens (decreased breakdown voltage, increased junction capacitance, instability)
Solution Approach 1:
The device isolation structure is divided into multiple stacked layers (first device isolation structure, second device isolation structure, third device isolation structure) with different stress characteristics. This segmentation allows each layer to contribute differently to stress management, enabling improved carrier mobility while maintaining device stability despite reduced device size
Solution Approach 2:
Different stress levels are applied to different regions of the device isolation structure. The first device isolation structure applies a first stress level, the second applies a second stress level, and the third applies a third stress level. This local differentiation of stress quality enables targeted improvement of carrier mobility in specific transistor regions without compromising overall device reliability
2Quantity of substance
If conventional stress application methods are used to improve carrier mobility, then carrier mobility can be improved, but it becomes difficult to achieve desired stress levels when gate material changes from hard tungsten silicide to soft tungsten
Solution Approach 1:
The device isolation structure serves as an intermediary element to apply stress to the transistor channel. Instead of relying on the gate material (which becomes too soft to provide adequate stress), the stacked device isolation structures act as a dedicated stress application mechanism that can maintain appropriate stress levels regardless of gate material changes
Solution Approach 2:
The stress levels in the device isolation structures are controlled by adjusting material composition and layer thickness parameters. By changing these parameters, different stress levels are achieved in each layer, enabling precise control over the stress applied to the transistor channel and improving carrier mobility
3Quantity of substance
If silicon germanium source/drain regions or Silicon-on-Insulator substrate are used to improve carrier mobility, then carrier mobility is improved, but manufacturing cost increases significantly
Solution Approach 1:
The invention uses standard silicon-based device isolation materials and conventional fabrication processes instead of expensive silicon germanium or Silicon-on-Insulator substrates. The stacked device isolation structures provide effective stress application using readily available materials and processes, significantly reducing manufacturing cost while still improving carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and operational characteristics of transistors by applying appropriate compressive stress levels to PMOS and NMOS transistors, reducing the adverse effects of the Short Channel Effect and enhancing gap-fill characteristics.
Implementation Method 1
the upper device isolation structure having a second compressive stress greater than the first compressive stress
Data Source
AI summary
The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower device isolation structure. The upper device isolation structure has a second compressive stress greater than the first compressive stress. A gate structure is disposed over the active region between the neighboring upper device isolation structures.