FinFET Device With Segmented SiGeO and Ge Layers
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Solution Overview
Problem
Existing FinFET devices and fabrication methods face challenges in achieving optimal performance due to limitations in material scaling and complexity in manufacturing, particularly in creating effective fin structures for enhanced transistor performance.
Innovation Solution
The method involves forming fin-like field-effect transistor (FinFET) devices with specific semiconductor material layers and processing steps, including epitaxial growth, thermal oxidation, and high-temperature annealing to create fin structures with a pure Ge feature and SiGeO layer, which reduces epitaxial defects and provides strain for improved electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing FinFET fabrication methods are used, then manufacturing can be maintained at current complexity levels, but device performance and electron mobility cannot be sufficiently improved
Solution Approach 1:
The fin structure is segmented into multiple semiconductor material layers (first semiconductor material layer, second semiconductor material layer, third semiconductor material layer) with different compositions and properties. Each layer serves a specific function: the first layer provides the base fin structure, the second layer introduces strain through different crystal structure, and the third layer enhances electron mobility. This segmentation allows optimization of device performance without requiring complete redesign of the fabrication process.
Solution Approach 2:
Different regions of the fin structure are assigned different material compositions and properties. The second semiconductor material layer is positioned specifically in the channel region where strain is needed to enhance carrier mobility, while other regions maintain their original material composition. This local differentiation of material quality enables targeted performance improvement without increasing overall fabrication complexity.
2Productivity
If planar transistors are used, then fabrication processes remain simple, but transistor performance and functional density cannot be sufficiently increased
Solution Approach 1:
The invention transitions from planar (2D) transistor structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and gate control without proportionally increasing the footprint area, thereby increasing functional density. The multi-layer semiconductor structure further enhances this by creating vertically stacked functional regions within the fin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance by concentrating Ge in the fin structures, reducing adverse substrate impacts, and enhancing channel mobility, thus addressing the limitations of existing FinFET devices and fabrication methods.
Implementation Method 1
applying a high temperature annealing to concentrate germanium in a center portion of an upper portion of the fin structure
Implementation Method 2
thermal oxidation
Data Source
AI summary
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.