Polysilicon FinFET 1T DRAM Cell Hole Trapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 1T DRAM cell devices with a capacitor structure face integration challenges with CPUs, slow memory capacity increase, and difficulty in three-dimensional stacking, while capacitorless 1T structures have shorter retention time and low gate channel control force.
Innovation Solution
A polysilicon-based 1T DRAM cell device with a FinFET structure is developed, where a polysilicon region captures holes in the channel area to improve retention time and increase gate channel control force, enabling batch processing with CPUs having FinFET structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a capacitor is added to form a 1T1C structure, then retention time is improved, but device complexity and integration difficulty increase
Solution Approach 1:
The patent removes the capacitor component from the conventional 1T1C DRAM structure, extracting only the essential storage function. By using a transistor-only structure with carefully engineered channel and doping regions, the capacitor is eliminated while maintaining data retention capability through the transistor's inherent charge storage in the channel region.
Solution Approach 2:
The transistor in the 1T0C structure performs multiple functions: it acts as the access transistor for read/write operations and simultaneously serves as the storage element through its channel region. This multi-functionality eliminates the need for a separate capacitor, reducing device complexity while maintaining retention time.
2Duration of action of moving object
If a capacitor is added to form a 1T1C structure, then retention time is improved, but ease of manufacture and batch processing with CPU decrease
Solution Approach 1:
The patent merges the memory cell and CPU transistor fabrication processes into a single unified flow. By using the same FinFET structure, material layers, and doping techniques for both CPU transistors and DRAM cells, the manufacturing processes are combined, enabling batch processing and simplifying integration while achieving adequate retention time without a capacitor.
3Device complexity
If a capacitorless 1T structure is used, then device complexity is reduced, but retention time becomes significantly shorter
Solution Approach 1:
The patent applies local quality by creating distinct regions within the transistor with different doping concentrations and channel characteristics. The channel region has specific doping levels optimized for charge storage, while source and drain regions have different doping profiles. This localized optimization of material properties enables adequate retention time in the capacitorless structure by enhancing charge confinement in the channel region without adding a capacitor.
4Ease of manufacture
If a conventional MOSFET structure is used, then ease of manufacture is maintained, but gate channel control force is low
Solution Approach 1:
The patent transitions from a planar MOSFET structure to a FinFET structure, adding a vertical dimension to the channel. The FinFET's three-dimensional configuration with fins extending vertically provides superior gate control over the channel through multiple sidewalls, significantly enhancing gate channel control force while maintaining compatibility with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves retention time and operating efficiency of the DRAM cell device, allowing for efficient integration and batch processing with FinFET-based CPUs.
Implementation Method 1
by intentionally forming a polysilicon region on the top of the channel area of the DRAM cell to physically capture and store the holes accumulated in the cell body
Implementation Method 2
a gate insulating film and a gate surrounding the channel region and the second semiconductor layer in a direction crossing the fin shape
Implementation Method 3
by raising the gate's channel control force with a FinFET structure to increase the operating efficiency
Data Source
AI summary
The present invention provides a polysilicon-based 1T DRAM cell device having a FinFET structure and its fabrication method. In the present invention, a semiconductor layer (for example, a polysilicon layer) having a relatively low crystallinity is intentionally formed on the upper layer of the active fin to physically trap the holes accumulated in the conventional cell body, thereby remarkably improving the retention time. A polysilicon-based 1T DRAM cell device having a FinFET structure can also increase the operating efficiency by raising the gate's channel control force and implement the batch process with the functional blocks in the CPU that already have the FinFET structure.