3D Memory Contact Structure to Prevent Bridge Defects

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Solution Overview

Problem

Existing semiconductor devices face challenges in increasing data storage capacity and improving integration and production yield due to issues such as bridge defects and mold collapse during the manufacturing process.

Innovation Solution

The semiconductor device incorporates a dam structure and a capping layer with different materials to prevent bridge defects and mold collapse, along with a through-contact plug design that enhances electrical connectivity and integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If connection patterns are arranged at different height levels to improve integration, then data storage capacity increases, but bridge defects and mold collapse occur during manufacturing

Engineering Contradiction:
Improvedata storage capacityVSAvoidproduction yield
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The connection patterns are divided into multiple layers (first connection pattern layer, second connection pattern layer) at different height levels, with each layer independently formed and protected by insulating layers. This segmentation allows complex three-dimensional routing while maintaining manufacturing reliability by preventing bridge defects through proper layer isolation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The capping layer is formed in advance to cover and protect the upper connection pattern before subsequent processing steps. This preliminary protective action prevents mold collapse and bridge defects during manufacturing by providing structural support and isolation, enabling high-density integration without compromising production yield.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If circuit elements are spaced closer to increase integration density, then data storage capacity increases, but leakage current increases

Engineering Contradiction:
Improveintegration densityVSAvoidleakage current
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

Insulating layers are introduced as intermediary structures between adjacent connection patterns and circuit elements. These insulating layers act as barriers that prevent electrical leakage while allowing the circuit elements to be spaced closer together, thereby increasing integration density without compromising electrical isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The device employs composite material structures combining conductive connection patterns with insulating materials at different height levels. This composite approach enables close spacing of circuit elements while the insulating components prevent leakage current, achieving high integration density with maintained electrical performance.

Inventive Principle:
Principle #40Composite materials

3Reliability

If through-contact plugs are used to enhance electrical connectivity, then integration improves, but device complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through-contact plugs serve multiple functions: they provide electrical connectivity between different layers, act as structural support elements, and enable simplified routing schemes. By consolidating these functions into a single structural element, the design achieves improved electrical connectivity without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12581657B2Semiconductor devices and data storage systems including the same
Publication Date: 2026.03.17 SAMSUNG ELECTRONICS CO LTD
  • US12581657B2 patent drawing
  • US12581657B2 patent drawing
  • US12581657B2 patent drawing

AI summary

A semiconductor device includes a peripheral circuit structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element, and a peripheral insulating structure on the circuit element, a memory cell structure on the peripheral circuit structure, the memory cell structure including interlayer insulating layers and gate electrodes alternately stacked on each other, an upper wiring, and a through-contact plug electrically connecting the upper wiring to an upper connection pattern in, which is in an uppermost position of the connection patterns relative to an upper surface of the substrate providing a base reference surface, wherein the peripheral circuit structure further includes a dam structure on the upper connection pattern, the peripheral insulating structure includes a first insulating layer on the circuit element and a side surface of the upper connection pattern and a second insulating layer, a capping layer, and a third insulating layer sequentially stacked on the first insulating layer, wherein the dam structure passes through the second insulating layer and contacts the upper connection pattern, and wherein the through-contact plug includes a lower portion passing through the dam structure and contacting the upper connection pattern and an upper portion on the lower portion.