3D Memory IC Control Scheme Using Self-Timing and Leakage Tracking
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Solution Overview
Problem
3D stacked chip devices face challenges with wire RC delay, increased leakage current, and process issues, particularly due to through-silicon via (TSV) overloading, which affect performance and efficiency.
Innovation Solution
A Semi-Master Slave scheme with self-timing control and a leakage current tracking circuit is introduced, allowing each chip layer to adjust timing based on process, voltage, and temperature variations, and utilizing a differential-TSV signal transfer to reduce design complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chip layers are stacked vertically to increase storage capacity, then storage capacity is improved, but wire RC delay and leakage current increase
Solution Approach 1:
The patent segments the control function by placing a master chip layer at the top and slave chip layers below it. The master chip layer contains the control circuit that generates timing signals, while slave chip layers have simplified structures without redundant control circuits. This segmentation reduces the number of control circuits across all layers, thereby reducing leakage current while maintaining the vertical stacking structure for increased storage capacity.
Solution Approach 2:
The patent extracts the control circuit functionality from individual chip layers and consolidates it into a single master chip layer. By removing control circuits from slave chip layers and retaining only necessary timing control elements, the patent reduces overall leakage current while preserving the essential control functions needed for memory operation.
2Adaptability or versatility
If each chip layer has its own control circuit for timing adjustment, then adaptability to process variations is improved, but device complexity increases
Solution Approach 1:
The patent segments control functionality hierarchically: the master chip layer contains the primary control circuit that generates timing signals, while slave chip layers contain only simplified timing control elements. This segmentation allows each layer to have basic timing adjustment capability while avoiding the complexity of full control circuits in every layer.
Solution Approach 2:
The patent implements self-timing control where slave chip layers automatically adjust their timing based on signals from the master chip layer without requiring complex control circuits. The timing adjustment is performed locally and autonomously by each chip layer, maintaining adaptability while minimizing overall system complexity.
3Speed
If through-silicon via (TSV) are used to connect stacked chips, then vertical interconnection is improved, but TSV overloading occurs causing performance degradation
Solution Approach 1:
The patent segments data transmission by implementing a master-slave architecture where the master chip layer transmits control signals through TSVs to slave chip layers. By organizing communication this way, the patent distributes the transmission load across multiple TSVs rather than concentrating all signals through a single path, reducing TSV overloading and improving reliability.
Solution Approach 2:
The patent uses partial action by having only the master chip layer generate control signals while slave chip layers respond to timing signals. This asymmetric design reduces the number of bidirectional TSV connections needed, thereby reducing TSV overloading and improving the reliability of vertical interconnections.
Data Source
AI summary
The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.