Digital Storage TRIZ Cases

A connector glues optical fibers directly to a ferrule while preserving the primary coating.

A memory tracking circuit uses dummy cells to delay word-line pulses, generating precise sense amplifier enable signals.

A neuromorphic computing device uses a second memory cell array with offset resistors to convert read currents into digital signals.

A semi-master slave control scheme for 3D memory ICs uses self-timing to adjust chip layer operations.

A non-volatile third dimensional memory array uses a two-terminal cross-point structure to enable simultaneous read and write operations.

Stray field applying layers generate internal magnetic fields to flip free layers, eliminating external magnets and reducing operating current.

Digital circuit filters preamble and post-amble transitions to reduce jitter errors during DDR2 data bursts.

Write assist circuitry boosts bitline voltage to improve data transfer.

A semiconductor device uses bank-level access detection circuits to track word line group signals for targeted memory refresh operations.

Adjusting sense amplifier transistor width-length ratio stabilizes memory write operations across varying thermal conditions.

A write buffer circuit clamps voltage levels at selected RRAM cells during write operations.

A dynamic throttling mechanism adjusts DRAM access bandwidth to prevent FIFO buffer overflow during memory tracing operations.

Dual-transistor keeper circuits track process variations and leakage currents to enhance reliability across fabrication tolerances.

Sampling row addresses identifies target rows, enabling targeted refresh operations that prevent row hammering without managing all accessed addresses.

Segmented internal command generators decode external signals to boost data transmission speeds while reducing power consumption in mobile systems.

A memory controller timing circuit adjusts clock signal phase based on calibration data to time communications with memory device ranks.

Write circuit monitoring cell current enables iterative voltage adjustment, preventing excessive writing and improving RRAM endurance.

Spare memory cells indicate when to refresh operational memory arrays, eliminating external cycle counters and reducing device complexity.

Independent dual select transistor gates eliminate gate-induced drain leakage in unselected ReRAM cells during programming operations.

Variable thickness supporter reduces electrode isolation trench formation risk while maintaining overall device thickness.

Isolates selected memory cells from digit lines during plate voltage transitions to reduce parasitic signal induction.

Parallel merging of resistive memory cells doubles the sense margin by increasing current difference, resolving resistance variation from DRAM fabrication.

Registers buffer data across bi-directional buses to eliminate clock cycle latency and maintain continuous data flow.

A semiconductor device adjusts reference voltage levels via flag signals to buffer external clock frequencies.

A word line fault detection circuit clamps floating lines to ground and compares encoded addresses against row addresses.

A sampling rate adjustor circuit monitors refresh operations to synchronize with actual memory access patterns.

A segmented internal voltage generator uses independent reference voltages for core voltage supply and discharge control.

Segmented redundant decoders select independent column signal lines for lower and upper blocks, repairing defects in both areas without shared line conflicts.

Dynamic random-access memory integrates artificial neural network neurons using shared sense amplifiers and column select lines to store synaptic weights.

Compensation transistors reduce required bit line split voltage from 70 mV to 10 mV, enabling higher memory density.

Random pulse generation circuits sample active row addresses to distribute activation, mitigating row hammering damage from frequent word line coupling.

Variable retention resistive memory cells reduce write energy consumption by matching storage duration to data needs.

A write assist circuit uses segmented power control circuits with switches of different drive strengths to alter SRAM bitcell inverter supply.

An intermediary switch transistor decouples column select from the word line, preventing half-select disturbance and improving cell stability.

Asymmetric SRAM bit cell reduces minimum read voltage below write voltage, achieving 30% power savings during frequent reads while maintaining stability.

A semiconductor memory apparatus uses a hammering control circuit to manage active operations on word lines.

Multiple bi-directional column interface buses split and interleave data to optimize transfer rates within a memory component.

A semiconductor apparatus uses a switch unit to manage current paths between write drivers and memory units during read and write operations.

A semiconductor memory control circuit fixes refresh latency during testing to simulate worst-case timing scenarios.

Merging global data lines into the main bit line metal layer reduces interconnect count while using pre-charged lines as shields to minimize interference noise.

A sense amplifier decouples from the power supply via reference lines and decoupling devices to isolate sensing nodes.

Replacing static SRAM and ROM with embedded DRAM cells enables post-silicon firmware updates, reducing manufacturing costs and turnaround time.

A semiconductor memory device outputs a self-refresh period level signal for precise measurement.

Segmented TCAM cells with integrated logical operations increase memory capacitance while reducing device complexity.

Read data strobe signal enables double data rate transfers on a reduced pin count memory bus, balancing high throughput against increased device complexity.

Segmenting the array into block units prevents parasitic voltage elevation on word lines during high-speed programming operations.

A shared delay circuit synchronizes sensing operations across memory banks by routing uniform delay signals through control circuitry.

Dynamic switches in the sense amplifier cancel offset noise, restoring the effective sensing margin for DRAM reliability.

A denoising scheme extracts soft information from PRAM read currents using wordline distance lookup tables to determine optimal reference currents.