Bi-directional Bus Data Transfer Latency Reduction
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Solution Overview
Problem
Bi-directional bus data transfer experiences inefficiency due to a required latency period of one full clock cycle, limiting the data transfer rate and causing inactivity during multiple clock cycles, which affects the overall performance of computing systems.
Innovation Solution
Implementing a method and apparatus with multiple bi-directional buses and registers that allow for simultaneous data transfer across both buses, enabling efficient data transfer between a memory controller and a single memory device by buffering write data and synchronizing commands, thereby overcoming latency constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred across a bi-directional bus, then data transfer occurs, but a latency period of one full clock cycle is required between transfers in opposite directions
Solution Approach 1:
The invention divides the data transfer process into separate write and read phases. Write data is transferred during a write phase, and read data is transferred during a read phase, preventing simultaneous bidirectional transfers that would cause latency conflicts.
Solution Approach 2:
Write data is buffered in advance in write data buffers before the corresponding write command is executed. This preliminary buffering allows the system to prepare data ahead of time, reducing waiting time and improving overall transfer efficiency.
2Device complexity
If a single bi-directional bus is used for data transfer, then the bus structure is simple, but the bus remains inactive during latency periods reducing productivity
Solution Approach 1:
The data bus is segmented into separate write data buffers and read data buffers, allowing independent transfer operations. This segmentation enables the bus to remain active continuously by separating conflicting write and read operations into different buffer structures.
Solution Approach 2:
Write data buffers act as intermediary storage structures between the data bus and the array. These buffers absorb the latency by holding write data until the array is ready, preventing bus idle time while maintaining data integrity.
3Productivity
If write data is transferred before the write command, then data transfer efficiency improves, but data may be lost if not properly synchronized
Solution Approach 1:
Write data is transferred to write data buffers in advance of the write command execution. This preliminary action improves efficiency by preparing data ahead of time while the buffer structure ensures data is held safely until the array is ready to receive it.
Solution Approach 2:
The system uses command timing and buffer management to provide feedback control. The write command timing is coordinated with the buffer status, ensuring data is transferred only when the array is ready, maintaining synchronization and reliability.
Data Source
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AI summary
A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.