Memory Row Hammering Defense via Random Pulse Sampling
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Solution Overview
Problem
As memory integration increases, the coupling effect between word lines leads to data damage in memory cells due to frequent activation, known as Row Hammering, which is exacerbated by external attacks.
Innovation Solution
A method and circuitry for randomly sampling and refreshing rows in a memory system, including a repair circuit to identify defective rows, a random pulse generation circuit, and a sampling circuit to select and store active addresses, thereby mitigating Row Hammering attacks by distributing activation across multiple rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If word line activation frequency is increased to improve memory access speed, then productivity is improved, but row hammering damage to neighboring memory cells increases
Solution Approach 1:
The patent applies preliminary action by proactively identifying frequently activated rows (potential row hammering targets) before damage occurs, and pre-refreshing their neighboring rows. The row hammering prevention circuit monitors activation patterns and performs preventive refreshing operations on adjacent rows before data deterioration can happen, thus protecting memory cells while maintaining high access speeds.
2Reliability
If random pulse activation is implemented to defend against row hammering, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the row hammering prevention functionality with the existing refresh circuitry. The row hammering prevention circuit shares the row address decoder and word line activation mechanisms with the normal memory operation circuit, and the random pulse generation is integrated into the existing refresh control logic. This consolidation allows reliable row hammering defense without proportionally increasing device complexity.
Data Source
AI summary
A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.


