Memory Controller Clock Timing Adjustment for DRAM Ranks
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Solution Overview
Problem
The timing of data communications between memory controllers and memory devices is challenging due to voltage and temperature variations, which cause previous calibrations to become obsolete, leading to system delays. Additionally, incorporating PLL or DLL on memory devices is not desirable due to power, die area, and system delay issues.
Innovation Solution
A memory controller with a clock generator to produce a first clock signal and a timing circuit to generate a second clock signal by adjusting the phase of the first clock signal based on calibration data and feedback from memory devices. This solution allows for precise timing adjustments without the need for PLL or DLL on memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequent calibrations are performed to maintain timing accuracy under voltage and temperature variations, then timing precision is improved, but system delay increases
Solution Approach 1:
The patent performs calibration in advance to determine timing adjustment values that compensate for voltage and temperature variations. These pre-calculated adjustment values are stored and applied during operation, eliminating the need for frequent real-time calibrations and reducing system delay while maintaining timing precision
Solution Approach 2:
The patent dynamically adjusts timing parameters based on detected voltage and temperature conditions. By monitoring environmental variables and applying corresponding pre-determined adjustments, the system adapts to changing conditions without requiring continuous recalibration, thus balancing precision with operational efficiency
2Measurement precision
If PLL or DLL is included on memory devices to maintain clock timing, then timing accuracy is improved, but power consumption and die area increase
Solution Approach 1:
The patent extracts the clock timing function from the memory device by having the memory controller generate and provide the clock signal directly to the memory device. This eliminates the need for PLL or DLL circuits on the memory device, reducing power consumption and die area while maintaining timing accuracy through the controller's calibration capabilities
Solution Approach 2:
The memory controller is designed to perform multiple functions including data transmission, reception, and clock signal generation with timing adjustments. By consolidating these functions in the controller, the system eliminates the need for separate clock generation circuits (PLL/DLL) in the memory device, reducing overall system complexity and power consumption
3Measurement precision
If PLL or DLL is included on memory devices to maintain clock timing, then timing accuracy is improved, but die area increases
Solution Approach 1:
The patent extracts the clock timing function from the memory device by having the memory controller generate and provide the clock signal directly to the memory device. This eliminates the need for PLL or DLL circuits on the memory device, reducing power consumption and die area while maintaining timing accuracy through the controller's calibration capabilities
Solution Approach 2:
The patent merges the clock generation and timing control functions into the memory controller, which already handles data transmission and reception. By combining these functions in a single component, the system eliminates the need for separate clock generation circuits in the memory device, thereby reducing die area while maintaining timing accuracy
Data Source
AI summary
A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.