Reduced Pin Count Memory Bus Interface with Read Data Strobe
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Solution Overview
Problem
Existing microcontroller and microprocessor bus interfaces face a challenge in balancing bus performance with the number of required bus signals, often necessitating a trade-off between pin count and data throughput, leading to either high latency with fewer signals or low speed with minimal pins.
Innovation Solution
A memory bus interface that includes a read data strobe, differential clock pair, and data bus for communication between host and peripheral devices, enabling Double Data Rate (DDR) data transfer and reducing the need for dedicated 'READY' or 'WAIT' signals, thus achieving a balance between performance and pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel peripheral bus interfaces are used for high speed data transmission, then data throughput is improved, but the number of required pins and signals increases
Solution Approach 1:
The patent combines multiple functions into fewer signals. The read data strobe signal serves both as a data validity indicator and a timing reference for double data rate transfers. The differential clock pair shares the clocking function across multiple data lines, reducing the total number of required pins while maintaining high throughput capability
Solution Approach 2:
The read data strobe signal performs multiple functions: it indicates when valid data is present on the bus, serves as a timing reference for DDR transfers, and enables the peripheral device to control the data transfer rhythm. This multi-functionality reduces the need for separate dedicated signals for each function
2Device complexity
If serial peripheral bus interfaces are used to minimize pin count, then the number of pins is reduced, but data rate decreases
Solution Approach 1:
The patent employs double data rate (DDR) transfers where data is transmitted on both the rising and falling edges of the clock signal. This periodic action on both edges of the clock cycle effectively doubles the data rate compared to single-edge sampling, achieving high throughput with minimal pins
Solution Approach 2:
The invention changes the timing parameter by using both rising and falling edges of the clock signal for data sampling. This parameter change from single-edge to multi-edge sampling increases the effective data rate without requiring additional pins or signals
Data Source
AI summary
A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.