Semiconductor Device Bank-Level Row Hammering Detection
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Solution Overview
Problem
As semiconductor devices increase in integration density, the coupling effect between word lines leads to row hammering, which damages data in memory cells before they can be refreshed, due to increased voltage fluctuations and electromagnetic interference.
Innovation Solution
A semiconductor device with a memory cell array that includes an access detection circuit and a refresh control circuit to detect row hammering by tracking access information signals for word line groups, allowing for targeted refresh operations to mitigate data degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between word lines is reduced to increase integration density, then the integration density is improved, but the coupling effect between adjacent word lines increases causing row hammering
Solution Approach 1:
The patent segments the memory device into multiple banks, with each bank containing independent memory cell arrays and control circuits. This segmentation isolates the coupling effects to individual banks, preventing row hammering from affecting the entire device. The bank-level structure allows localized refresh operations without impacting other banks, thus maintaining high integration density while mitigating coupling effects.
Solution Approach 2:
The patent introduces a bank control circuit as an intermediary between the address decoding circuit and the memory cell arrays. This intermediary monitors access patterns to each bank and triggers targeted refresh operations when row hammering is detected. The bank control circuit acts as a mediator that prevents the harmful coupling effects from propagating throughout the entire memory device by implementing localized corrective actions.
2Reliability
If additional refresh operations are performed on adjacent word lines to mitigate row hammering, then data reliability is improved, but device complexity and operation time increase
Solution Approach 1:
The patent implements local quality by performing refresh operations only on the specific banks that are susceptible to row hammering, rather than refreshing the entire memory device. The bank control circuit identifies affected banks based on access patterns and applies refresh operations locally to those banks only. This localized approach maintains data reliability while reducing the overall complexity and time required for refresh operations compared to full-device refresh.
Solution Approach 2:
The patent applies partial action by implementing refresh operations on a subset of banks rather than all banks. The bank control circuit determines which banks require refresh based on access pattern analysis, and performs refresh operations only on those specific banks. This partial approach is sufficient to mitigate row hammering effects while avoiding the excessive complexity and time overhead of refreshing the entire memory device.
3Reliability
If access patterns are monitored and tracked to detect row hammering, then data protection capability is improved, but the complexity of control circuits increases
Solution Approach 1:
The patent segments the access detection function into bank-level monitoring units, with each bank having its own control circuit that tracks access patterns independently. This segmentation allows the system to monitor access patterns effectively for row hammering detection while keeping the complexity of each individual control circuit manageable. The modular bank-level structure distributes the monitoring complexity across multiple independent units rather than requiring a single complex centralized controller.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes data loss by identifying and addressing row hammering through targeted refresh operations, reducing the capacity and area required for storage blocks and lowering fabrication costs.
Implementation Method 1
an access detection circuit configured for storing N low-order bit signals contained in N access information signals indicating the numbers of accesses to N word line groups, and generating an access information signal corresponding to the current input word line group address signal among the N access information signals
Implementation Method 2
a refresh control circuit configured for generating a target group address signal required for a refresh operation of the memory cell array, based on the word line group address signal, the access information signal and a refresh control signal
Data Source
AI summary
A semiconductor device may include: a low-order bit storage block configured for storing N low-order bit signals contained in N access information signals based on an access address signal, the N access information signals indicating the numbers of accesses to N access target blocks, and generating an indication signal indicating whether a low-order bit signal corresponding to the current input access address signal among the N low-order bit signals has reached a predetermined value; a high-order bit storage block configured for storing M high-order bit signals contained in M access information signals among the N access information signals based on an allocation control signal; and a high-order bit control block configured for generating the allocation control signal corresponding to positions in which the M high-order bit signals are to be stored, based on the access address signal and the indication signal.