SRAM Cell Stability via Switch Transistor Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SRAM cells face stability issues due to increased variability and noise margin degradation at aggressively scaled technologies, particularly during half select operating mode, leading to potential disturbance of adjacent cells during write operations.
Innovation Solution
Incorporating a switch transistor coupled to the column select line in SRAM cells to isolate them from the word line during read and write operations, preventing half select disturbance and enhancing cell stability without significant area penalty or complexity increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If SRAM cells are aggressively scaled to increase integration density, then area is reduced, but stability and noise margin deteriorate due to increased variability
Solution Approach 1:
The patent segments the control mechanism by introducing a separate column select line (CSL) independent from the word line (WL). This segmentation allows independent control of bit line isolation, enabling the cell to enter deep standby mode where both pass-gate transistors are fully off, thus preventing half-select disturbance while maintaining scaled dimensions
Solution Approach 2:
The patent introduces an intermediary switch transistor (e.g., M160) controlled by the column select line that acts as a mediator between the word line and the pass-gate transistors. This intermediary provides an additional isolation layer that enhances stability by ensuring complete disconnection during half-select conditions, resolving the stability issue without increasing cell area
2Area of stationary object
If conventional 6-T SRAM cell structure is used, then area is minimized, but half select disturbance occurs during write operations affecting adjacent cells
Solution Approach 1:
The patent extracts the column select function from the conventional word line control mechanism. By taking out the column select line (CSL) as an independent control signal, the patent enables separate control of bit line isolation, allowing the cell to be completely isolated from bit line disturbances during half-select conditions while maintaining the compact 6-T structure
Solution Approach 2:
The patent introduces dynamic control through the column select line that can independently modulate the isolation state of pass-gate transistors. This dynamic control mechanism allows the cell to adapt its isolation level based on operational mode (read, write, or standby), effectively preventing half-select disturbance without adding static structural complexity
Data Source
AI summary
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.