RRAM Write Buffer Circuit Clamps Voltage to Prevent Overstress
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Solution Overview
Problem
Resistive random access memory (RRAM) devices face overstress issues during write operations when using a current-driven mode, which can lead to damage due to high voltage levels, necessitating a solution to prevent such overstress.
Innovation Solution
A circuit comprising a current generator and a voltage generator with PMOS transistors acts as a write buffer, clamping the voltage level at a selected cell to prevent overstress by controlling the on/off state of transistors based on the resistance state of the cell, ensuring that the voltage does not exceed a threshold, thereby maintaining the integrity of the memory array during state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current-driven mode (CDM) is used to write RRAM device, then better on/off ratio and tighter resistance distribution are achieved, but over-stress occurs causing damage to the RRAM device
Solution Approach 1:
A write buffer circuit is introduced as an intermediary between the current generator and the RRAM cell. The write buffer includes a first PMOS transistor connected in parallel with the RRAM cell, controlled by a write buffer control signal. This intermediary structure allows the beneficial current-driven write operation to proceed while the PMOS transistor acts as a protective element that can be activated to prevent over-stress damage when needed.
Solution Approach 2:
The invention dynamically changes the electrical parameters (voltage and current) applied to the RRAM cell during write operations. By adjusting the write buffer control signal, the system can modify the current path and voltage distribution in real-time, preventing the cell from experiencing damaging voltage levels while still achieving the desired resistance state transitions.
2Speed
If high current is applied to switch RRAM cell between resistance states, then faster write speed is achieved, but voltage spikes cause overstress and potential damage
Solution Approach 1:
The write buffer control signal is activated in advance or concurrently with the write current application. This preliminary anti-action prepares the protective PMOS transistor to counteract any potential voltage spikes before they can cause damage, allowing high current to flow for fast writing while maintaining device safety through preemptive protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively prevents overstress in RRAM devices by maintaining a stable voltage level during write operations, ensuring the longevity and reliability of the memory array by ensuring that the voltage does not exceed a threshold, thus preventing damage and maintaining the integrity of the memory array during state transitions.
Implementation Method 1
A circuit comprising a current generator and a voltage generator with PMOS transistors acts as a write buffer, clamping the voltage level at a selected cell to prevent overstress by controlling the on/off state of transistors based on the resistance state of the cell
Data Source
AI summary
A circuit includes a current generator and a voltage generator. The current generator is configured to generate a predetermined current flowing toward a selected cell in a memory array via a node during a write operation. The voltage generator is configured to generate a predetermined voltage. The voltage level at the node is clamped at a predetermined value associated with the predetermined voltage as the selected cell is switched between a low resistance state and a high resistance state during the write operation.