Non-Volatile 3D Memory with Dual-Port Cross-Point Array
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Solution Overview
Problem
Conventional semiconductor memory technologies face limitations in volatility, area efficiency, and access speed, particularly in dual port memory systems, which restrict their ability to provide stable, high-capacity, low-power memory solutions for modern electronic devices.
Innovation Solution
The development of a non-volatile, dual port third-dimensional memory system using a two-terminal cross-point memory array with mixed valence conductive oxides and electrolytic tunnel barriers, allowing for simultaneous read and write operations without the need for an erase operation, and enabling efficient data storage with adjustable resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional semiconductor memory is used, then volatility is avoided with non-volatile memory, but area efficiency deteriorates
Solution Approach 1:
The patent transitions from planar two-dimensional memory architecture to three-dimensional vertical stacking architecture. Multiple memory layers are stacked vertically, allowing data to be stored in the third dimension (height) rather than only in the plane. This dimensional change enables significantly higher storage density per unit area while maintaining non-volatile characteristics, directly resolving the contradiction between data stability and area efficiency.
2Speed
If dual port memory is implemented in conventional technology, then access speed is improved, but write operation latency increases due to erase requirements
Solution Approach 1:
The patent extracts and removes the erase operation requirement from the write operation sequence. By using a three-terminal memory cell architecture with independent word lines and bit lines, the system enables direct write operations without requiring a separate erase phase. This extraction of the erase step eliminates the associated latency, allowing fast write operations that match read speeds, thereby resolving the contradiction between access speed and write latency.
3Adaptability or versatility
If three-terminal memory configuration is used, then power supply flexibility is limited, but if two-terminal configuration is used, then power consumption reduction is achieved
Solution Approach 1:
The patent merges the source and drain terminals into a single electrode structure, creating a two-terminal memory cell. This consolidation reduces the number of terminals from three to two, simplifying the circuit architecture and reducing power consumption. The merged terminal configuration maintains full functionality for both read and write operations while achieving lower power requirements, effectively resolving the contradiction between voltage flexibility and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances memory capacity, reduces power consumption, and eliminates latency associated with write operations, providing stable and efficient data storage with improved access speeds and reduced area requirements.
Implementation Method 1
The memory element can include an electrolytic tunnel barrier and a mixed valence conductive oxide. A voltage drop across the electrolytic tunnel barrier can cause an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide and into the electrolytic tunnel barrier.
Implementation Method 2
When certain mixed valence conductive oxides (e.g., praseodymium-calcium-manganese-oxygen perovskites and lanthanum-nickel-oxygen perovskites) change valence, their conductivity changes.
Data Source
AI summary
Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.