Memory Cell Isolation During Plate Voltage Transitions

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Solution Overview

Problem

Memory devices with a plate coupled to multiple digit and word lines face issues of parasitic signal induction during access operations, leading to data errors and inefficiencies due to unintended coupling, which affects the reliability and power consumption of the devices.

Innovation Solution

The implementation of techniques to isolate the selected memory cell from the selected digit line during state transitions of the plate and unselected digit lines, reducing parasitic signals by decoupling the memory cell during plate and digit line transitions, thereby minimizing disturbances to unselected memory cells and improving access operation efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a plate is coupled with multiple digit lines and word lines to increase memory cell density, then memory cell density is improved, but parasitic signal induction occurs during access operations leading to data errors

Engineering Contradiction:

Improvememory cell densityVSAvoiddata accuracy

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the coupled lines into two distinct groups: a first set of coupled lines and a second set of coupled lines. By separating the lines into different groups and applying different voltage transitions to each group, the patent prevents parasitic signal induction while maintaining the high-density memory cell configuration. This segmentation allows independent control of voltage transitions on different line groups, eliminating the parasitic coupling issue.

Inventive Principle:

Principle #1Segmentation

2Speed

If voltage transitions are applied to plate and digit lines during access operations to enable memory access, then access speed is improved, but parasitic signals are induced on unselected memory cells causing disturbances

Engineering Contradiction:

Improveaccess operation speedVSAvoidparasitic signal disturbance

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent divides the coupled lines into first and second sets, allowing differential voltage transition application. The first set of coupled lines receives a first voltage transition while the second set receives a second voltage transition, enabling fast access operations without inducing parasitic signals on unselected memory cells.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different voltage transition characteristics to different groups of lines based on their selection status. Selected lines receive voltage transitions optimized for fast access, while unselected lines receive different voltage transitions that prevent parasitic signal induction, achieving local optimization of both speed and signal integrity.

Inventive Principle:

Principle #3Local quality

3Device complexity

If a single plate is coupled with multiple digit lines to reduce the number of plate drivers, then device complexity is reduced, but unintended coupling between components occurs during access operations

Engineering Contradiction:

Improvenumber of plate driversVSAvoidunintended coupling

Core Design Contradiction:

Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the coupled lines into distinct first and second sets, enabling independent voltage control of each set. This segmentation allows a single plate to couple with multiple digit lines without causing unintended coupling, as different voltage transitions can be applied to different line sets, preventing parasitic signal induction while maintaining reduced device complexity.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces parasitic signal-induced errors and enhances the reliability and power efficiency of memory device operations by isolating the selected memory cell during state transitions, allowing for faster and more precise control over memory access operations.

Implementation Method 1

unintended coupling between various components (e.g., memory cells, digit lines, word lines) may occur during an access operation. In some cases, when the plate or a digit line transitions from a first voltage to a second voltage, parasitic signals may be induced on other memory cells, digit lines, and/or word lines.

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS11881252B2Techniques for accessing an array of memory cells to reduce parasitic coupling

Publication Date: 2024.01.23 MICRON TECHNOLOGY INC

AI summary

Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.