ReRAM Array Select Transistor GIDL Reduction
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Solution Overview
Problem
Prior-art ReRAM memory cells experience gate-induced drain leakage (GIDL) in unselected memory cells during programming and erasing operations due to shared gate connections for series-connected select transistors.
Innovation Solution
The implementation of ReRAM memory cells with two series-connected n-channel select transistors, each having a gate connected to a separate control line, allowing for independent control of the transistors and reducing GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If two series-connected select transistors share a common gate connection to a word line, then high-voltage stress between bit line and source line is mitigated, but gate-induced drain leakage (GIDL) occurs in unselected memory cells
Solution Approach 1:
The common gate connection is segmented into two separate gate connections, each controlled by independent word lines (WL1 and WL2). This allows selective control of each transistor's gate voltage, enabling the first transistor to be turned off (Vgs=0V) while the second transistor remains on (Vgs>0V) during unselected states, thereby eliminating GIDL while maintaining voltage stress mitigation
Solution Approach 2:
The gate control is made dynamic by introducing independent word lines that can be selectively activated. During unselected states, WL1 is set to 0V to turn off the first transistor and prevent GIDL, while WL2 maintains appropriate voltage to keep the second transistor conductive. This dynamic control adapts to different operational states (selected/unselected, read/write) to optimize performance
2Object-generated harmful factors
If separate control lines are used for each select transistor gate, then GIDL is reduced, but device complexity increases
Solution Approach 1:
The dual-word line control structure serves multiple functions: it eliminates GIDL in unselected cells, enables selective programming of specific memory cells, and maintains compatibility with existing ReRAM cell architectures. The same control mechanism benefits all memory cells in the array simultaneously, making the increased complexity worthwhile through its multifunctional advantages
Data Source
AI summary
A ReRAM memory array includes ReRAM memory cells and a select circuit having first and second series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for programming, the bit line coupled to the ReRAM memory cell(s) to be programmed is biased at a first voltage potential and the source line coupled to the ReRAM memory cell(s) to be programmed is biased at a second voltage potential less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program the ReRAM device. The gates of first and second series-connected select transistors of ReRAM memory cell(s) to be programmed are supplied with positive voltage pulses. The gates of second series-connected select transistors of respective ReRAM memory cell(s) unselected for programming are supplied with a voltage potential insufficient to turn them on.