DRAM Embedded ANN Architecture for Reconfigurable Neural Networks
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Solution Overview
Problem
Existing artificial neural network (ANN) implementations in semiconductor technology are limited by the inability to reconfigure networks after initial training, leading to inflexibility and inefficiency due to physical size constraints and memory requirements for large networks.
Innovation Solution
A dynamic random-access memory (DRAM) with embedded ANN functionality that allows for user-configurable neuron connections and integrated training within the memory device, utilizing a high-density, parallel architecture to store weights and biases, enabling efficient reprogramming and updating of neural networks without hardware replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory elements such as SRAM or volatile registers are used to create a programmable ANN, then the ANN can be reconfigured by changing weights and biases, but the memory elements are physically large, limit the feasible size of the ANN, and may also limit the flexibility of the connections between neurons
Solution Approach 1:
The patent transitions from using SRAM or volatile registers to using DRAM cells, changing the memory technology parameter to achieve higher density. This allows the same physical area to store more synaptic weights, enabling larger ANN configurations while maintaining reprogrammability through standard DRAM write operations.
2Productivity
If a specific network is hard-coded into semiconductor technology for high computing efficiency, then computing efficiency is improved, but the ability to subsequently reconfigure the network by changing weights, biases, or interconnections is lost
Solution Approach 1:
The patent creates a universal ANN platform using DRAM that can perform both high-speed computing operations and reconfiguration of network parameters. The DRAM array serves multiple functions: storing synaptic weights, holding intermediate computations, and allowing dynamic reprogramming of the network architecture, eliminating the need to choose between efficiency and adaptability.
3Loss of energy
If the neural network is fully integrated into the memory device, then data transfer between memory and processor is eliminated, but the device complexity increases
Solution Approach 1:
The patent merges the neural network computation functions directly into the DRAM memory device by utilizing the existing DRAM array and sense amplifier infrastructure. The sense amplifiers perform the neural summation function, and the DRAM cells store both weights and intermediate results, eliminating separate computation hardware and reducing overall system complexity despite the integrated functionality.
Data Source
AI summary
A highly configurable, extremely dense, high speed and low power artificial neural network is presented. The architecture may utilize DRAM cells for their density and high endurance to store weight and bias values. A number of primary sense amplifiers along with column select lines (CSLs), local data lines (LDLs), and sense circuitry may comprise a single neuron. Since the data in the primary sense amplifiers can be updated with a new row activation, the same hardware can be reused for many different neurons. The result is a large amount of neurons that can be connected by the user. Training can be done in hardware by actively varying weights and monitoring cost. The network can be run and trained at high speed since processing and/or data transfer that needs to be performed can be minimized.