Neuromorphic Computing Device Offset Resistor Compensation
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Solution Overview
Problem
Neuromorphic computing devices face accuracy decreases due to temperature and time dependency of resistive memory cells, leading to unreliable computations and inference.
Innovation Solution
Incorporating a second memory cell array with offset resistors connected in parallel, using the same resistive material as the first memory cell array, to convert read currents into digital signals, thereby mitigating temperature and time dependency, and ensuring consistent resistance across offset resistors for enhanced sensing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistive memory cells are used for neuromorphic computing, then computational efficiency is improved, but accuracy of inference deteriorates due to temperature and time dependency
Solution Approach 1:
A second memory cell array is created as a copy of the first memory cell array, using the same resistive memory cells with identical resistive material. This copy is used exclusively for generating reference currents that mirror the temperature and time dependency characteristics of the computational array, enabling accurate compensation without affecting the primary computational function.
Solution Approach 2:
Offset resistors are introduced as intermediary elements connected in parallel with the reference memory cells. These offset resistors act as mediators to adjust and fine-tune the reference currents, allowing precise matching of the reference characteristics to the computational array's behavior under varying temperature and time conditions.
2Reliability
If offset resistors are added to compensate for temperature and time dependency, then accuracy of inference is improved, but device complexity increases
Solution Approach 1:
The reference memory cells and offset resistors are merged into a single integrated second memory cell array that mirrors the structure of the first array. This unified structure generates reference currents that inherently account for temperature and time dependency, eliminating the need for separate compensation circuits and reducing overall system complexity.
Solution Approach 2:
The second memory cell array is designed with homogeneous characteristics identical to the first array, using the same resistive memory cells and configuration. This homogeneity ensures that the reference currents automatically match the computational array's temperature and time dependency, providing accurate compensation without requiring complex heterogeneous compensation mechanisms.
3Manufacturing precision
If different materials are used for offset resistors, then resistance matching becomes difficult, but manufacturing precision can be improved
Solution Approach 1:
The same resistive material is used in both the first and second memory cell arrays, ensuring homogeneous electrical characteristics. This material consistency automatically provides temperature and time dependency matching between computational and reference cells, eliminating the need for complex resistance matching processes that would be required with different materials.
Solution Approach 2:
The second memory cell array is created as an exact copy of the first array, including identical resistive material and cell structure. This copying approach ensures inherent matching of temperature and time dependency characteristics, simplifying the manufacturing process by eliminating the need for specialized resistance matching techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the accuracy of computations and inference by matching the temperature and time dependency of the second memory cell array with the first, while simplifying the manufacturing process and improving sensing performance.
Implementation Method 1
A first memory cell array including a plurality of resistive memory cells, stores a plurality of data, generates a plurality of read currents based on a plurality of input signals and the plurality of data
Implementation Method 2
capable of preventing the decrease in the accuracy of inference due to temperature and/or time dependency of resistive memory cells
Data Source
AI summary
A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.