Spare Memory Cells for Refresh Timing Detection
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Solution Overview
Problem
Existing memory technologies face challenges in accurately determining when to refresh memory cells to prevent read disturb, leading to erroneous data sensing and reduced performance, especially in high-density memory devices, and current solutions increase complexity and cost.
Innovation Solution
The implementation of spare memory cells that are deterministically made to fail with a higher sensing voltage pulse, indicating when to refresh non-spare memory cells before they are affected by read disturb, thereby preventing erroneous data sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If program/read cycle counters are used to determine when to refresh memory cells, then refresh timing can be tracked, but device complexity and cost increase
Solution Approach 1:
The memory cells themselves serve as the measurement mechanism through their resistance state changes. The cells autonomously indicate when refresh is needed through their own physical property degradation, eliminating the need for external counters or control logic to track read cycles.
Solution Approach 2:
Spare memory cells act as intermediaries that are deliberately degraded at a faster rate than operational cells. These spare cells serve as a proxy indicator system, where their failure state signals when the operational memory cells require refresh, without directly monitoring each operational cell.
2Measurement precision
If program/read cycle counters are used to determine when to refresh memory cells, then refresh timing can be tracked, but cost increases
Solution Approach 1:
Spare memory cells are intentionally designed with shorter operational lifetimes than the main memory array. These disposable-like cells are sacrificed to provide refresh timing information, reducing the need for expensive counter circuits or complex control logic in the main memory system.
Solution Approach 2:
The memory cells inherently provide their own aging and degradation information through resistance state changes. This self-reporting mechanism eliminates the need for external tracking infrastructure, reducing manufacturing costs associated with counters and control logic.
3Duration of action of moving object
If higher sensing voltage pulses are applied to spare memory cells, then spare cells fail faster providing refresh indication, but risk of affecting non-spare memory cells increases
Solution Approach 1:
The memory array is segmented into operational memory cells and separate spare memory cells. This physical and functional separation allows the spare cells to be subjected to different stress conditions (higher voltage pulses) without directly affecting the integrity of the operational cells, as long as the spare cells are properly isolated during sensing operations.
Solution Approach 2:
Different voltage stress levels are applied to different segments of the memory array. Spare cells receive higher voltage pulses to accelerate their degradation, while operational cells receive standard voltage levels. This localized quality differentiation enables accelerated aging of spare cells without compromising operational cell reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate determination of when to refresh memory cells without using program/read cycle counters, reducing complexity and cost while maintaining memory performance and extending its lifetime.
Implementation Method 1
A state of a resistance variable memory cell can be determined by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.