Shared Delay Circuit for Memory Bank Sensing Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory devices like DRAM, manufacturing variations lead to mismatched delays between memory banks, causing increased error rates and reduced performance due to inconsistent sensing operations.
Innovation Solution
A shared delay circuit and delay path control circuitry are used to generate and control delay signals, ensuring a uniform sensing delay period across all memory banks, thereby synchronizing the start of sense amplifiers with the row active command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate delay circuits are used for each memory bank, then delay adjustment for each bank is possible, but device complexity increases
Solution Approach 1:
The patent merges multiple separate delay circuits into a single shared delay circuit that serves all memory banks. The shared delay circuit generates delay signals that are distributed to multiple memory banks through delay path control circuitry, reducing overall device complexity while maintaining consistent delay timing across all banks.
Solution Approach 2:
The patent segments the delay function into two parts: a shared delay circuit that generates base delay signals, and delay path control circuitry that routes and adjusts these signals for individual memory banks. This segmentation allows a single shared circuit to provide bank-specific delay control without requiring separate delay circuits for each bank.
2Ease of manufacture
If manufacturing processes are simplified, then ease of manufacture improves, but manufacturing precision of delay circuits deteriorates
Solution Approach 1:
The patent introduces delay amount detection circuitry that monitors the delay amounts of different memory banks and generates detection signals. These detection signals are used to adjust the delay path control circuitry, creating a feedback loop that compensates for manufacturing variations and ensures consistent delay timing across all memory banks despite process variations.
Solution Approach 2:
The patent uses parameter adjustment through the delay path control circuitry to compensate for manufacturing variations. By dynamically adjusting delay path parameters based on detection signals, the system achieves precise delay matching without requiring extremely tight manufacturing tolerances for the shared delay circuit components.
Data Source
AI summary
A memory device includes a plurality of memory banks and a sensing delay circuit. Each of the memory banks is activated by a row active command and is configured to perform a sensing operation based on a sensing enable signal. The sensing delay circuit, that includes a shared delay circuit and a delay path control circuitry, may delay a start of the sensing enable signal by a sensing delay period from an assertion of the row active command. The shared delay circuit is shared to the memory banks and may generate a plurality of delay signals based on the assertion of the row active command. The delay path control circuitry configured to control an electrical path between the shared delay circuit and the memory banks based on the row active command and the plurality of delay signals to output the sensing enable signal to the memory bank.