Semiconductor Memory Refresh Control Circuit Timing
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Solution Overview
Problem
Conventional semiconductor memory devices with dynamic type memory cells require complex timing control to prevent interference between self-refresh and read/write operations, leading to increased testing costs and uncertainty in device quality due to random refresh timing.
Innovation Solution
A control circuit that fixes latency by generating refresh operations directly before or after read/write operations during testing, allowing for controlled simulation of worst-case timing scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If refresh timing is controlled randomly by timer timeout, then device operates in normal mode, but testing complexity and cost increase due to inability to control timing scenarios
Solution Approach 1:
The refresh control circuit dynamically switches between two operational modes: normal mode where refresh timing is determined by timer timeout, and test mode where refresh timing is controlled by test control signals. This dynamic adaptability allows the device to accommodate both normal operation requirements and testing requirements without compromising either functionality.
Solution Approach 2:
A test control circuit acts as an intermediary between the external tester and the refresh control circuit. This intermediary receives test control signals from external testers and translates them into internal control signals that regulate refresh operation timing, thereby enabling precise control of refresh timing during testing while maintaining normal operation unaffected.
2Device complexity
If refresh operation timing cannot be controlled, then device structure remains simple, but testing reliability decreases due to inability to simulate worst-case scenarios
Solution Approach 1:
The control system is segmented into distinct functional blocks: a normal operation path governed by timer timeout, and a test operation path governed by test control signals. The refresh control circuit selectively activates one path based on operational mode, allowing simple normal operation while enabling comprehensive testing through the dedicated test control path.
Solution Approach 2:
The system changes the control parameter for refresh timing based on operational mode. In normal mode, the control parameter is timer timeout intervals; in test mode, the control parameter becomes test control signal timing. This parameter switching enables precise control of refresh timing during testing to simulate various operational scenarios including worst-case conditions.
3Ease of operation
If refresh and read/write operations occur independently, then operation autonomy is maintained, but interference between operations may cause malfunctions
Solution Approach 1:
The refresh control circuit incorporates feedback mechanisms that monitor the timing relationships between refresh operations and read/write operations. When potential interference is detected or anticipated, the circuit adjusts refresh timing under test control signal guidance to prevent malfunctions, thereby maintaining operational reliability while preserving the autonomy of individual operations.
Solution Approach 2:
During testing, the system applies preliminary anti-action by using test control signals to proactively schedule refresh operations at specific timing relative to read/write operations. This preemptive control prevents interference conditions from occurring in the first place, rather than reacting to malfunctions after they occur, thereby ensuring operation reliability.
Data Source
AI summary
Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read/write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read/write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.