Keeper Circuit Compensation for Memory Process Variations

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Solution Overview

Problem

Conventional keeper circuits in bit-line sensing memories face challenges in tracking fabrication process variations and leakage currents, leading to performance degradation and reduced yield due to differences in NMOS and PMOS transistor speeds.

Innovation Solution

An apparatus and method that include a keeper circuit with a PMOS transistor coupled to a sensing circuit, an NMOS transistor to track discharge leakage currents, and multiple PMOS transistors connected to bit-lines, allowing for compensation of fabrication process variations by controlling the connection and disconnection of these transistors based on feedback signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional keeper circuits with only PMOS transistors are used, then the circuit structure is simple, but the keeper circuit cannot track NMOS transistor process variations leading to performance degradation

Engineering Contradiction:

Improvekeeper circuit structureVSAvoidtracking of process variations

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent combines both PMOS and NMOS transistors in the keeper circuit to create a dual-transistor keeper that can track process variations of both transistor types. The NMOS transistor is added to track NMOS bit-cell variations while the PMOS transistor tracks PMOS variations, allowing the keeper circuit to compensate for process variations in both device types simultaneously.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback mechanisms where the keeper circuit continuously monitors and adjusts its operation based on the actual state of bit-cells. The keeper circuit uses feedback from the bit-cell performance to dynamically adjust the keeper current, ensuring optimal tracking of process variations throughout fabrication tolerances.

Inventive Principle:

Principle #23Feedback

2Reliability

If the keeper circuit is made stronger to support slower PMOS transistors, then the keeper current increases, but discharge leakage increases especially at lower voltages

Engineering Contradiction:

Improverobustness for slow devicesVSAvoiddischarge leakage

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent employs dynamic keeper circuits that can adjust their strength based on operating conditions. The keeper circuit transitions between different operational states (e.g., strong keeper mode and weak keeper mode) depending on the detected bit-cell performance and voltage conditions, allowing optimal performance across different process corners and voltage levels.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes key parameters of the keeper circuit including transistor sizes, threshold voltages, and operating currents to optimize performance for different scenarios. By adjusting these parameters, the keeper circuit can adapt to support slower devices when needed while minimizing leakage when not required.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the keeper circuit size and number of PMOS transistor stacks are increased, then the keeper current increases, but the area occupied by the keeper circuit increases

Engineering Contradiction:

Improvekeeper current capabilityVSAvoidkeeper circuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by using different transistor sizes and configurations in different parts of the keeper circuit. Rather than uniformly increasing all transistor sizes, the design selectively sizes transistors based on their specific functional requirements, achieving the necessary keeper current capability with minimal area overhead.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent uses composite transistor structures combining PMOS and NMOS devices in strategic configurations. This composite approach allows the keeper circuit to achieve enhanced current capability through the synergistic interaction of different transistor types rather than simply scaling up single transistor sizes, thereby reducing area requirements.

Inventive Principle:

Principle #40Composite materials

4Productivity

If finFET technology is used to achieve higher density and speed, then system on-chip density and speed improve, but fabrication process variation increases

Engineering Contradiction:

Improvesystem on-chip density and speedVSAvoidfabrication process variation

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements self-service mechanisms where the keeper circuit automatically compensates for finFET process variations without requiring external calibration or adjustment. The dual-transistor keeper structure inherently tracks and compensates for process variations through its design, allowing the memory system to maintain performance across fabrication tolerances autonomously.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10998018B1Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory

Publication Date: 2021.05.04 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.