Semiconductor Memory Row Hammering Control Circuit
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Solution Overview
Problem
As the number of memory cells in semiconductor memory apparatuses increases, the interval between word lines decreases, leading to row hammering issues where data leakage occurs due to unstable word line states, necessitating additional circuits for detection and refresh operations, which complicates design and increases complexity.
Innovation Solution
Incorporating a hammering control circuit that manages active operations on word lines by storing counting values in row hammer memory cells, allowing for detection and refresh operations with minimal circuit area, thereby reducing the complexity and area required for circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve storage capacity, then the circuit area per memory cell is reduced, but the interval between word lines decreases causing row hammering issues
Solution Approach 1:
The memory cell array is divided into multiple banks, with each bank containing both normal memory cells and row hammer memory cells. This segmentation allows the system to handle row hammering issues locally within each bank rather than requiring system-wide complex protection circuits.
Solution Approach 2:
Row hammer memory cells are introduced as intermediary elements between normal memory cells. These special memory cells are used to detect and count active operations on adjacent word lines, serving as sensors that trigger refresh operations when row hammering is detected.
2Reliability
If additional circuits are added to detect and refresh row hammering, then data integrity is improved, but device complexity increases
Solution Approach 1:
The row hammer memory cells serve multiple functions: they act as both normal storage cells and as detection sensors for row hammering. The same memory cell structure is used for both data storage and for counting active operations, eliminating the need for separate detection circuits.
Solution Approach 2:
The memory system performs self-diagnosis and self-refresh through the row hammer memory cells. When row hammering is detected, the system automatically triggers refresh operations on the affected word lines without requiring external intervention or complex control logic.
3Measurement precision
If row hammer memory cells are used to count active operations, then detection precision is improved, but the area of stationary object increases
Solution Approach 1:
The counting function is merged into the existing memory cell structure. The row hammer memory cells use the same basic memory cell components (transistors and capacitors) as normal memory cells, combining the storage function with the counting function in a single integrated structure.
Solution Approach 2:
The memory cell parameters are optimized to serve dual purposes. The same physical structure that stores data in normal memory cells is used to store counting values in row hammer memory cells, changing the functional parameter rather than the physical structure.
Data Source
AI summary
A semiconductor memory apparatus includes a first memory cell array, a second memory cell array, and a hammering control circuit. The first memory cell array includes a first row hammer memory cell. The second memory cell array includes a second row hammer memory cell. The hammering control circuit controls the number of active operations on a first word line to be stored in the second row hammer memory cell and controls the number of active operations on a second word line to be stored in the first row hammer memory cell.