SRAM Write Assist Circuit Using Segmented Power Control
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Solution Overview
Problem
Conventional write assist techniques for SRAM face challenges in improving write margin without increasing dynamic power consumption, particularly due to contention between NMOS and PMOS pull-down and pull-up devices.
Innovation Solution
A write assist circuit is introduced, utilizing a set of switches with different drive strengths in the power control circuits connected to SRAM bitcell inverters. These switches are controlled by input data on bit lines to alter the power supply or ground supply to the inverters, assisting in writing data into the SRAM without contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write assist techniques use NMOS pull down and PMOS pull up to pull down supply voltage based on data present on bit lines, then write margin is improved, but dynamic power consumption increases due to contention between NMOS and PMOS devices
Solution Approach 1:
The write assist circuit is segmented into two separate power control circuits: one controlling the supply voltage (VDD) and another controlling the ground voltage (VSS). Each circuit independently manages one side of the voltage control, eliminating the contention that occurs when both NMOS and PMOS devices operate simultaneously in conventional approaches.
Solution Approach 2:
The invention extracts the ground control function from the conventional supply voltage control approach. By introducing a separate ground control circuit that independently manages VSS, the design removes the need for simultaneous NMOS and PMOS operation, thereby eliminating the power consumption issue while maintaining write assist functionality.
2Productivity
If advanced technology nodes are used for miniaturization, then device integration is improved, but threshold voltage and size variations increase affecting bitcell strength
Solution Approach 1:
The invention implements dynamic voltage control by using time-varying control signals (write assist signals) that adjust the supply and ground voltages during the write operation. This dynamic adjustment compensates for process variations in threshold voltage and device size, ensuring reliable write operations in advanced technology nodes where such variations are more pronounced.
Solution Approach 2:
The invention changes the voltage parameters (VDD and VSS) dynamically during write operations to compensate for process variations. By adjusting these voltage levels based on the write assist signals, the circuit maintains adequate bitcell strength despite variations in threshold voltage and device dimensions inherent in miniaturized advanced technology nodes.
3Reliability
If write assist techniques are used to improve write margin, then write performance is enhanced, but operating voltage, cycle time, or data retention may be affected
Solution Approach 1:
The write assist circuit employs periodic control signals that are activated only during write operations. The supply and ground control circuits receive periodic write assist signals that temporarily adjust voltages during writing, then return to normal operating levels, ensuring that data retention and operating voltage stability are maintained when write operations are not in progress.
Solution Approach 2:
The invention applies preliminary control by using write assist signals to preemptively adjust supply and ground voltages before the actual write operation occurs. This preliminary voltage adjustment ensures that the bitcell is in the optimal state for writing without compromising the overall operating voltage stability or data retention characteristics of the SRAM cell.
Data Source
AI summary
A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.