SRAM Write Assist Circuit for Low Voltage Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Write operations for SRAM storage cells become unreliable at lower operation supply voltages due to variations in circuit characteristics, as the PMOS pull-up transistor is strengthened and the NMOS pass gate is weakened, preventing reliable data transfer.
Innovation Solution
A write assist circuitry is initialized to reduce the column supply voltage and boost the bitline voltage below the low supply voltage, weakening the PMOS pull-up transistor and strengthening the NMOS pass gate, thereby improving write reliability without changing transistor sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operation supply voltage is reduced to improve energy efficiency, then energy efficiency is improved, but write reliability deteriorates due to PMOS pull-up transistor strengthening and NMOS pass gate weakening
Solution Approach 1:
The write assist circuit pre-charges the bitline to a voltage higher than the supply voltage before the write operation begins. This preliminary voltage boosting ensures that when the NMOS pass gate activates, there is sufficient voltage differential to overcome the strengthened PMOS pull-up transistor even at reduced supply voltages, thereby maintaining write reliability while enabling lower operating voltages for improved energy efficiency
Solution Approach 2:
The invention dynamically changes the bitline voltage parameter by boosting it above the supply voltage level during write operations. This parameter modification compensates for the weakened NMOS pass gate effect at lower supply voltages, allowing the system to operate at reduced voltages (improving energy efficiency) while maintaining adequate write capability (preserving reliability)
2Reliability
If transistor sizes are changed to improve write reliability, then write reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of modifying transistor physical dimensions, the invention changes the electrical parameter (bitline voltage) to achieve write reliability improvement. This approach avoids the complexity of redesigning transistor sizes and the associated manufacturing challenges, while still effectively compensating for process variations and aging effects
Solution Approach 2:
The write assist circuit acts as an intermediary mechanism that mediates between the supply voltage and the storage cell. Rather than directly modifying the storage cell structure (transistor sizes), it introduces a voltage boosting mechanism that simplifies the overall design while improving write reliability
3Stability of the object's composition
If PMOS pull-up transistor strength is increased due to circuit variations, then retention is improved, but write operation reliability deteriorates as NMOS pass gate becomes weaker
Solution Approach 1:
The bitline is pre-charged to a voltage higher than the supply voltage before the write operation. This preliminary action creates a sufficient voltage differential that can overcome the strengthened PMOS pull-up transistor, enabling reliable data transfer despite the imbalance caused by circuit variations or aging
Solution Approach 2:
The write assist circuit applies a counteracting voltage boost to the bitline that preemptively compensates for the excessive PMOS pull-up strength. This preliminary anti-action neutralizes the adverse effect of circuit variations before the write operation begins, allowing both strong retention (from PMOS) and reliable writes (from boosted bitline voltage) to coexist
Data Source
AI summary
A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.