Semiconductor Memory Device Hierarchical Bit Line Architecture
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Solution Overview
Problem
Conventional hierarchical bit line architectures in semiconductor memory devices with cross-point sub bit lines lead to increased interconnect layers, signal delay, power supply drop, and noise due to interference between main bit lines, which degrades performance and increases costs.
Innovation Solution
The architecture is modified by dividing the main memory array into two sub-memory arrays with twice the number of sub bit lines, allowing main bit lines and global data lines to be formed in the same interconnect layer, and arranging global data lines between main bit lines to act as shields, reducing interference noise without increasing the number of interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If main bit lines and sub bit lines are formed in separate metal interconnect layers following conventional hierarchical architecture, then noise isolation between bit lines is improved, but the number of interconnect layers increases and manufacturing complexity increases
Solution Approach 1:
The patent combines main bit lines and global data lines into the same metal interconnect layer, eliminating the need for separate layers. This merging reduces the total number of interconnect layers while maintaining noise isolation through strategic routing and shielding configurations within the unified layer structure.
Solution Approach 2:
The metal interconnect layer is designed to serve multiple functions simultaneously: it carries both main bit lines for memory access and global data lines for data output, while also providing noise shielding capabilities. This multi-functionality eliminates the need for dedicated separate layers for each function.
2Object-affected harmful factors
If more metal interconnect layers are added to separate main bit lines from global data lines, then signal interference is reduced, but manufacturing costs increase and process complexity increases
Solution Approach 1:
The patent merges main bit lines and global data lines into the same metal interconnect layer, reducing the total layer count and associated manufacturing costs. The design compensates for potential interference through careful routing strategies and shielding implementations within the unified layer.
Solution Approach 2:
The patent converts potential noise interference into beneficial shielding effects by strategically positioning global data lines to act as shields for main bit lines. The return signal paths of global data lines are used to create Faraday cage effects that protect sensitive bit line signals from external noise.
3Quantity of substance
If the number of sub bit lines is increased to cover more memory cells, then memory density is improved, but parasitic capacitance on main bit lines increases and signal quality degrades
Solution Approach 1:
The patent segments the memory array into multiple sub-memory arrays, each with its own set of sub bit lines that converge to shared main bit lines. This segmentation allows for better distribution and management of parasitic capacitance loads on each main bit line, preventing excessive capacitance accumulation while maintaining high memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces bit line noise and improves read and sense operating characteristics by minimizing interference between main bit lines, maintaining performance while reducing costs by not increasing the number of interconnect layers.
Implementation Method 1
interference noise between the main bit lines from a coupling capacitor
Implementation Method 2
interference noise between main bit lines
Data Source
AI summary
In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.