Memory Tracking Circuit for Read Margin and Access Time
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Solution Overview
Problem
Memory circuits face reading errors due to insufficient read margin caused by weak driving ability of memory cell arrays and inadequate delay in sense amplifier enable signals, especially when voltage levels change, leading to increased access time and error probability.
Innovation Solution
A memory circuit with a tracking circuit that includes dummy cells and a dummy bit line, where the dummy cells are cascaded transistors that delay the word-line pulse signal to generate a sense amplifier enable signal, allowing for extended discharge time of the bit line and improving data bit detection accuracy across varying voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay time TD is extended to increase the read margin M, then the read margin is improved, but the access time of the memory circuit is increased
Solution Approach 1:
The tracking circuit dynamically adjusts the delay period TD based on the voltage level of the voltage source. When voltage decreases, the delay period automatically extends to maintain adequate read margin. This dynamic adaptation resolves the contradiction by making the delay time variable rather than fixed, allowing the system to optimize between read margin and access time based on operating conditions.
2Use of energy by moving object
If the voltage level of the voltage source is lowered to reduce power consumption, then the power consumption is reduced, but the read margin decreases and reading errors increase
Solution Approach 1:
The tracking circuit monitors the voltage level and provides feedback control for the delay period. When voltage drops, the tracking circuit automatically increases the delay period to compensate for the reduced cell current and maintain adequate read margin. This feedback mechanism allows the system to operate at lower voltages for reduced power consumption while maintaining reliability through automatic compensation.
3Ease of manufacture
If standard-threshold voltage transistors are used in the tracking circuit, then manufacturing costs are reduced, but the delay period may be insufficient when voltage levels change
Solution Approach 1:
The tracking circuit uses dummy cells that copy the structure and characteristics of the actual memory cells. This copying approach allows the tracking circuit to accurately track voltage-level-dependent timing characteristics using standard-threshold transistors, achieving both manufacturing simplicity and timing accuracy through structural replication rather than using expensive high-threshold transistors.
Data Source
AI summary
The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells, a dummy bit line, and an inverter. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for pulling down the voltage of the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled between the dummy cells and the inverter. The inverter inverts the voltage of the dummy bit line to generate the sense amplifier enable signal.