Dynamic DRAM Bandwidth Throttling for FIFO Overflow Prevention
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Solution Overview
Problem
The existing memory systems face challenges in managing the bandwidth of input data relative to the storage system, leading to FIFO buffer overflows due to the faster processing speed of CPUs compared to DRAM, resulting in memory trace data loss and performance inefficiencies.
Innovation Solution
Implementing a dynamic throttling mechanism that monitors the FIFO buffer for overflow, adjusts the operating mode to exclude refresh commands from memory trace data collection, and increases the DRAM refresh rate to prevent buffer overflow, thereby ensuring continuous data collection and improving memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU operates at high speed to process millions of instructions per second, then processing productivity is improved, but the memory system cannot keep up with the CPU speed, causing FIFO buffer overflow and data loss
Solution Approach 1:
The patent implements dynamic throttling of DRAM access bandwidth based on real-time FIFO buffer status. The memory tracer system adjusts the rate of memory access requests dynamically - when the FIFO buffer approaches capacity, the system reduces the access rate to prevent overflow, and increases it when buffer space is available. This dynamic adjustment resolves the contradiction by allowing high CPU productivity while maintaining data integrity through adaptive bandwidth control.
Solution Approach 2:
The system employs feedback mechanisms where the memory tracer system continuously monitors FIFO buffer occupancy levels and uses this information to regulate DRAM access bandwidth. The feedback loop detects buffer status and adjusts memory access rates accordingly, ensuring that the memory subsystem operates within capacity limits while maximizing data collection. This feedback-controlled approach maintains reliability without permanently limiting CPU productivity.
2Loss of information
If the memory access bandwidth is increased to match CPU speed, then data collection completeness is improved, but the FIFO buffer overflows due to excessive input data rate
Solution Approach 1:
The patent applies partial action by selectively throttling DRAM access bandwidth only when necessary to prevent FIFO overflow, rather than continuously limiting the memory subsystem. The system allows memory access bandwidth to reach levels that would match CPU speed when buffer capacity permits, but applies partial throttling only during high-load periods. This ensures data completeness is maintained without permanently sacrificing memory processing throughput.
Solution Approach 2:
The system dynamically changes the bandwidth parameter of DRAM access based on FIFO buffer status. When buffer occupancy is low, the memory access bandwidth parameter is increased to capture more trace data. When buffer occupancy approaches capacity, the bandwidth parameter is reduced to prevent overflow. This parameter adjustment strategy resolves the contradiction between data completeness and processing throughput by adapting bandwidth to current system conditions.
3Loss of information
If the FIFO buffer size is increased to accommodate higher data rates, then data loss is reduced, but system complexity and resource consumption increase
Solution Approach 1:
The patent extracts the bandwidth control function from the buffer management system and implements it as a separate throttling mechanism in the memory tracer. Rather than increasing buffer size to handle all possible data rates, the system maintains a fixed, manageable buffer size and extracts the excess data rate control to a dedicated throttling component. This separation reduces buffer management complexity while maintaining data retention capacity through active rate control.
Data Source
AI summary
A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.