Unbalanced SRAM Bit Cell for Low Power Read Operations
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Solution Overview
Problem
Conventional SRAM arrays operate at the same voltage for both read and write operations, leading to inefficient power consumption, especially since data is read more frequently than written, necessitating a solution to reduce power usage while maintaining stability.
Innovation Solution
Designing an unbalanced SRAM bit with stronger pullup transistors and weaker passgate transistors, adjusting their dimensions and threshold voltages to allow for reduced read voltage and increased write voltage, thereby optimizing the SRAM array for lower power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SRAM arrays operate at the same voltage for both read and write operations, then the circuit design is simple and symmetric, but power consumption is inefficient especially during frequent read operations
Solution Approach 1:
The patent applies asymmetry by designing the SRAM bit cell with unequal transistor dimensions - specifically, the pullup transistors are made stronger (larger width-to-length ratio) than the passgate transistors. This asymmetric design allows the read operation to use a lower voltage than the write operation, reducing power consumption during frequent read operations while maintaining write capability at higher voltage
Solution Approach 2:
The patent implements local quality by optimizing different transistor components within the SRAM bit cell with different characteristics. The pullup transistors are designed with specific dimensions to enable low-voltage read operations, while the passgate transistors are designed with different dimensions to ensure proper write operations at higher voltage, allowing each component to be optimized for its specific function
2Use of energy by moving object
If the minimum read voltage is reduced to save power, then power consumption decreases, but read stability may be compromised
Solution Approach 1:
The patent changes the critical parameter of transistor strength by adjusting the width-to-length ratio of the pullup transistors. By making the pullup transistors stronger (increasing their drive current capability), the circuit can maintain stable read operations at lower voltages, thus reducing power consumption while preserving read stability through parameter optimization
3Reliability
If the minimum write voltage is increased to improve write stability, then write reliability improves, but power consumption increases
Solution Approach 1:
The patent segments the voltage operation into two distinct levels: a lower voltage for read operations and a higher voltage for write operations. This segmentation allows the SRAM array to operate efficiently at low voltage during frequent reads, while occasionally switching to higher voltage for writes, thereby reducing overall power consumption while maintaining write stability when needed
Data Source
AI summary
An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.