Semiconductor Apparatus Switching for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional PCRAMs face issues with long data storage times and potential fail bits due to parasitic capacitance in the current path during write operations, which affects the efficiency and reliability of data storage.
Innovation Solution
A semiconductor apparatus with a switch unit that controls current paths between the write driver, sense amplifier unit, and memory unit, using specific select signals and control signals to manage connections and disconnections during read and write operations, thereby minimizing parasitic capacitance and improving drivability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sense amplifier unit remains connected to the memory unit during write operation, then data can be sensed, but parasitic capacitance accumulates causing long storage time and fail bits
Solution Approach 1:
The sense amplifier unit is enabled before the write operation starts (in preparation phase) and disabled when the write operation starts. This preliminary enabling allows the sense amplifier to be ready to sense data immediately after write, while the switch unit disconnects it during write to prevent parasitic capacitance accumulation. The control unit coordinates timing signals to achieve this sequence.
Solution Approach 2:
The switch unit dynamically controls the connection state between the sense amplifier unit and memory unit based on operation phase. During write operation, the switch disconnects them; during read operation, the switch connects them. This dynamic switching prevents parasitic capacitance buildup while maintaining data accessibility when needed.
2Ease of operation
If the sense amplifier unit is enabled during write operation, then data sensing is ready, but parasitic capacitance causes fail bits
Solution Approach 1:
The sense amplifier unit is enabled in advance before the write operation begins, preparing the data sensing circuitry. However, the switch unit simultaneously disconnects the sense amplifier from the memory unit during the write operation to prevent parasitic capacitance accumulation. This allows the sense amplifier to be operationally ready without being electrically connected during the critical write phase.
Solution Approach 2:
The control system segments the operation into distinct phases with different connection states. The switch unit separates the sense amplifier unit from the memory unit during write operation, creating independent operational domains. This segmentation allows the sense amplifier to be enabled for readiness without being connected, preventing interference during write.
3Reliability
If the switch unit controls current paths dynamically, then parasitic capacitance is minimized, but control circuit complexity increases
Solution Approach 1:
The switch unit serves multiple functions: it controls the connection between sense amplifier and memory unit, manages current paths during write and read operations, and prevents parasitic capacitance accumulation. By consolidating these control functions into a single multi-functional switch unit coordinated by the control unit, the patent reduces overall system complexity while achieving reliable data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces data storage time and prevents fail bits by effectively managing current paths, enhancing the efficiency and reliability of data storage in PCRAMs.
Implementation Method 1
The PCRAM causes a reversible phase change between the crystalline state and the amorphous state of GST, using Joule heat generated after applying a current or voltage under a specific condition for GST.
Implementation Method 2
The phase change material may include a material which can transition into an amorphous state or crystalline state depending on a temperature condition.
Data Source
AI summary
A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.